Manduchi Gabriele, Rigoni Andrea, Trevisan Luca, Patton Tommaso
Consorzio RFX, Corso Stati Uniti, 4, 35127 Padova, Italy.
Sensors (Basel). 2024 Sep 23;24(18):6155. doi: 10.3390/s24186155.
Proper timing synchronization is important when data from sensors are acquired by different devices. This paper proposes a simple but effective solution for System on Chip (SoC) architectures that integrates a general-purpose Field Programmable Gate Array (FPGA) with a CPU. The proposed approach relies on a network synchronization protocol implemented in software, such as Network Time Protocol (NTP) or Precision Time Protocol (PTP), and uses the FPGA to generate a clock reference that is maintained in step with the synchronized system clock. The clock generated by the FPGA is obtained from the FPGA oscillator via appropriate fractional clock division. Clock drift is avoided via a software program that periodically compares the FPGA and the system counters, respectively, and adjusts the fractional clock divider in order to slightly adjust the FPGA clock frequency using a Proportional Integral controller. A specific implementation is presented on the RedPitaya platform, generating a 1 MHz clock in step with the NTP synchronized system clock. The presented system has been used in a distributed data acquisition system for fast transient recording in the neutral beam test facility for the ITER nuclear fusion experiment.
当不同设备采集来自传感器的数据时，正确的定时同步非常重要。本文针对将通用现场可编程门阵列（FPGA）与CPU集成的片上系统（SoC）架构提出了一种简单而有效的解决方案。所提出的方法依赖于在软件中实现的网络同步协议，如网络时间协议（NTP）或精确时间协议（PTP），并使用FPGA生成与同步系统时钟保持同步的时钟参考。FPGA生成的时钟通过适当的分数分频从FPGA振荡器获得。通过一个软件程序避免时钟漂移，该程序分别定期比较FPGA和系统计数器，并使用比例积分控制器调整分数分频器，以便略微调整FPGA时钟频率。在RedPitaya平台上给出了一个具体实现，生成与NTP同步系统时钟同步的1MHz时钟。所展示的系统已用于分布式数据采集系统，用于ITER核聚变实验中性束测试设施中的快速瞬态记录。
