Luc Le Xuan, Eul Lee Han, Choa Sung-Hoon
Graduate School of Nano IT Design Fusion, Seoul National University of Science and Technology, Seoul, 01811, Republic of Korea.
Department of Manufacturing Systems and Design Engineering, Seoul National University of Science and Technology, Seoul, 01811, Republic of Korea.
J Nanosci Nanotechnol. 2021 May 1;21(5):2949-2958. doi: 10.1166/jnn.2021.19132.
Recently, fine pitch wafer level packaging (WLP) technologies have drawn a great attention in the semiconductor industries. WLP technology uses various interconnection structures including microbumps and through-silicon-vias (TSVs). To increase yield and reduce cost, there is an increasing demand for wafer level testing. Contact behavior between probe and interconnection structure is a very important factor affecting the reliability and performance of wafer testing. In this study, with a MEMS vertical probe, we performed systematic numerical analysis of the deformation behavior of various interconnection structures, including solder bump, copper (Cu) pillar bump, solder capper Cu bump, and TSV. During probing, the solder ball showed the largest deformation. The Cu pillar bump also exhibited relatively large deformation. The Cu bump began to deform at OD of 10 m. At OD of 20 m, bump pillar was compressed, and the height of the bump decreased by 8.3%. The deformation behavior of the solder capped Cu bump was similar to that of the solder ball. At OD of 20 m, the solder and Cu bumps were largely deformed, and the total height was reduced by 11%. The TSV structure showed the lowest deformation, but exerted the largest stress on the probe. In particular, copper protrusion at the outer edge of the via was observed, and very large shear stress was generated between the via and the silicon oxide layer. In summary, when probing various interconnection structures, the probe stress is less than that when using an aluminum pad. On the other hand, deformation of the structure is a critical issue. In order to minimize damage to the interconnection structure, smaller size probes or less overdrive should be used. This study will provide important guidelines for performing wafer-level testing and minimizing damage of probes and interconnection structures.
近年来，精细间距晶圆级封装（WLP）技术在半导体行业引起了广泛关注。WLP技术采用了包括微凸点和硅通孔（TSV）在内的各种互连结构。为了提高良率并降低成本，对晶圆级测试的需求日益增加。探针与互连结构之间的接触行为是影响晶圆测试可靠性和性能的一个非常重要的因素。在本研究中，我们使用MEMS垂直探针，对包括焊料凸点、铜（Cu）柱形凸点、焊料覆盖铜凸点和TSV在内的各种互连结构的变形行为进行了系统的数值分析。在探测过程中，焊球的变形最大。铜柱形凸点也表现出相对较大的变形。铜凸点在外径为10μm时开始变形。在外径为20μm时，凸点柱被压缩，凸点高度降低了8.3%。焊料覆盖铜凸点的变形行为与焊球相似。在外径为20μm时，焊料和铜凸点发生了很大变形，总高度降低了11%。TSV结构的变形最小，但对探针施加的应力最大。特别是，在通孔的外边缘观察到铜突出，并且在通孔和氧化硅层之间产生了非常大的剪切应力。总之，在探测各种互连结构时，探针应力小于使用铝焊盘时的应力。另一方面，结构的变形是一个关键问题。为了使互连结构的损坏最小化，应使用尺寸更小的探针或减小过驱动。本研究将为进行晶圆级测试以及使探针和互连结构的损坏最小化提供重要指导。
