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一种用于高通量像素条(PS)传感器的8.72微瓦低噪声宽带宽前端电子学设计。

An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors.

作者信息

Jérôme Folla Kamdem, Evariste Wembe Tafo, Bernard Essimbi Zobo, Crespo Maria Liz, Cicuttin Andres, Reaz Mamun Bin Ibne, Bhuiyan Mohammad Arif Sobhan

机构信息

Energy, Electrical and Electronics Systems, Department of Physics, University of Yaoundé I, P.O. Box 812, Yaoundé 222, Cameroon.

Multidisciplinary Laboratory (MLAB), International Centre for Theoretical Physics (ICTP), Via Beirut 31, 34100 Trieste, Italy.

出版信息

Sensors (Basel). 2021 Mar 4;21(5):1760. doi: 10.3390/s21051760.

Abstract

The front-end electronics (FEE) of the Compact Muon Solenoid (CMS) is needed very low power consumption and higher readout bandwidth to match the low power requirement of its Short Strip application-specific integrated circuits (ASIC) (SSA) and to handle a large number of pileup events in the High-Luminosity Large Hadron Collider (LHC). A low-noise, wide bandwidth, and ultra-low power FEE for the pixel-strip sensor of the CMS has been designed and simulated in a 0.35 µm Complementary Metal Oxide Semiconductor (CMOS) process. The design comprises a Charge Sensitive Amplifier (CSA) and a fast Capacitor-Resistor-Resistor-Capacitor (CR-RC) pulse shaper (PS). A compact structure of the CSA circuit has been analyzed and designed for high throughput purposes. Analytical calculations were performed to achieve at least 998 MHz gain bandwidth, and then overcome pileup issue in the High-Luminosity LHC. The spice simulations prove that the circuit can achieve 88 dB dc-gain while exhibiting up to 1 GHz gain-bandwidth product (GBP). The stability of the design was guaranteed with an 82-degree phase margin while 214 ns optimal shaping time was extracted for low-power purposes. The robustness of the design against radiations was performed and the amplitude resolution of the proposed front-end was controlled at 1.87% FWHM (full width half maximum). The circuit has been designed to handle up to 280 fC input charge pulses with 2 pF maximum sensor capacitance. In good agreement with the analytical calculations, simulations outcomes were validated by post-layout simulations results, which provided a baseline gain of 546.56 mV/MeV and 920.66 mV/MeV, respectively, for the CSA and the shaping module while the ENC (Equivalent Noise Charge) of the device was controlled at 37.6 e at 0 pF with a noise slope of 16.32 e/pF. Moreover, the proposed circuit dissipates very low power which is only 8.72 µW from a 3.3 V supply and the compact layout occupied just 0.0205 mm die area.

摘要

紧凑型μ子螺线管(CMS)的前端电子设备(FEE)需要非常低的功耗和更高的读出带宽,以匹配其短条专用集成电路(ASIC)(SSA)的低功耗要求,并处理高亮度大型强子对撞机(LHC)中的大量叠加事件。已采用0.35μm互补金属氧化物半导体(CMOS)工艺设计并模拟了用于CMS像素条传感器的低噪声、宽带宽和超低功耗FEE。该设计包括一个电荷灵敏放大器(CSA)和一个快速电容-电阻-电阻-电容(CR-RC)脉冲整形器(PS)。为了实现高吞吐量,对CSA电路的紧凑结构进行了分析和设计。进行了分析计算,以实现至少998MHz的增益带宽,进而克服高亮度LHC中的叠加问题。Spice仿真证明,该电路可实现88dB的直流增益,同时展现出高达1GHz的增益带宽积(GBP)。在保证82度相位裕度的情况下确保了设计的稳定性,同时为实现低功耗提取了214ns的最佳整形时间。对该设计的抗辐射鲁棒性进行了测试,所提出前端的幅度分辨率控制在1.87%半高宽(FWHM)。该电路设计用于处理高达280fC的输入电荷脉冲,最大传感器电容为2pF。与分析计算结果高度吻合,布局后仿真结果验证了仿真结果,该结果分别为CSA和整形模块提供了546.56mV/MeV和920.66mV/MeV的基线增益,而器件的等效噪声电荷(ENC)在0pF时控制在37.6e,噪声斜率为16.32e/pF。此外,所提出的电路功耗非常低,从3.3V电源获取的功耗仅为8.72μW,紧凑的布局仅占用0.0205mm²的芯片面积。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/b618/7962011/5b776774fe4c/sensors-21-01760-g001.jpg

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