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迈向单层二硫化钼的低温固体源合成

Toward Low-Temperature Solid-Source Synthesis of Monolayer MoS.

作者信息

Tang Alvin, Kumar Aravindh, Jaikissoon Marc, Saraswat Krishna, Wong H-S Philip, Pop Eric

机构信息

Department of Electrical Engineering, Stanford University, Stanford, California 94305, United States.

Department of Materials Science and Engineering, Stanford University, Stanford, California 94305, United States.

出版信息

ACS Appl Mater Interfaces. 2021 Sep 8;13(35):41866-41874. doi: 10.1021/acsami.1c06812. Epub 2021 Aug 24.

Abstract

Two-dimensional (2D) semiconductors have been proposed for heterogeneous integration with existing silicon technology; however, their chemical vapor deposition (CVD) growth temperatures are often too high. Here, we demonstrate direct CVD solid-source precursor synthesis of continuous monolayer (1L) MoS films at 560 °C in 50 min, within the 450-to-600 °C, 2 h thermal budget window required for back-end-of-the-line compatibility with modern silicon technology. Transistor measurements reveal on-state current up to ∼140 μA/μm at 1 V drain-to-source voltage for 100 nm channel lengths, the highest reported to date for 1L MoS grown below 600 °C using solid-source precursors. The effective mobility from transfer length method test structures is 29 ± 5 cm V s at 6.1 × 10 cm electron density, which is comparable to mobilities reported from films grown at higher temperatures. The results of this work provide a path toward the realization of high-quality, thermal-budget-compatible 2D semiconductors for heterogeneous integration with silicon manufacturing.

摘要

二维(2D)半导体已被提议用于与现有硅技术进行异质集成;然而,它们的化学气相沉积(CVD)生长温度通常过高。在此,我们展示了在560°C下50分钟内通过CVD固体源前驱体直接合成连续单层(1L)MoS薄膜,该温度处于与现代硅技术进行后端兼容所需的450至600°C、2小时热预算窗口内。晶体管测量结果表明,对于100nm沟道长度,在1V漏源电压下的导通电流高达约140μA/μm,这是迄今为止使用固体源前驱体在600°C以下生长的1L MoS所报道的最高值。通过转移长度法测试结构测得的有效迁移率在电子密度为6.1×10cm时为29±5cm²V⁻¹s⁻¹,这与在较高温度下生长的薄膜所报道的迁移率相当。这项工作的结果为实现与硅制造异质集成的高质量、热预算兼容的2D半导体提供了一条途径。

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