Hong Nianmin, Zhang Yinong, Sun Quan, Fan Wenjie, Li Menglu, Xie Meng, Fu Wenxin
Key Laboratory of Science and Technology on High-Tech Polymer Materials, Institute of Chemistry, Chinese Academy of Sciences, Beijing 100190, China.
School of Chemistry and Chemical Engineering, University of Chinese Academy of Sciences, Beijing 100049, China.
Materials (Basel). 2021 Aug 25;14(17):4827. doi: 10.3390/ma14174827.
Since the application of silicon materials in electronic devices in the 1950s, microprocessors are continuously getting smaller, faster, smarter, and larger in data storage capacity. One important factor that makes progress possible is decreasing the dielectric constant of the insulating layer within the integrated circuit (IC). Nevertheless, the evolution of interlayer dielectrics (ILDs) is not driven by a single factor. At first, the objective was to reduce the dielectric constant (k). Reduction of the dielectric constant of a material can be accomplished by selecting chemical bonds with low polarizability and introducing porosity. Moving from silicon dioxide, silsesquioxane-based materials, and silica-based materials to porous silica materials, the industry has been able to reduce the ILDs' dielectric constant from 4.5 to as low as 1.5. However, porous ILDs are mechanically weak, thermally unstable, and poorly compatible with other materials, which gives them the tendency to absorb chemicals, moisture, etc. All these features create many challenges for the integration of IC during the dual-damascene process, with plasma-induced damage (PID) being the most devastating one. Since the discovery of porous materials, the industry has shifted its focus from decreasing ILDs' dielectric constant to overcoming these integration challenges. More supplementary precursors (such as Si-C-Si structured compounds), deposition processes (such as NH plasma treatment), and post porosity plasma protection treatment (P4) were invented to solve integration-related challenges. Herein, we present the evolution of interlayer dielectric materials driven by the following three aspects, classification of dielectric materials, deposition methods, and key issues encountered and solved during the integration phase. We aim to provide a brief overview of the development of low-k dielectric materials over the past few decades.
自20世纪50年代硅材料应用于电子设备以来,微处理器在不断变小、变快、变智能,且数据存储容量不断增大。使这一进步成为可能的一个重要因素是降低集成电路(IC)内绝缘层的介电常数。然而,层间电介质(ILD)的发展并非由单一因素驱动。起初,目标是降低介电常数(k)。降低材料的介电常数可以通过选择低极化率的化学键并引入孔隙率来实现。从二氧化硅、倍半硅氧烷基材料和二氧化硅基材料发展到多孔二氧化硅材料,该行业已能够将ILD的介电常数从4.5降至低至1.5。然而,多孔ILD机械性能较弱、热稳定性差且与其他材料的兼容性不佳,这使其具有吸收化学物质、水分等的倾向。所有这些特性在双大马士革工艺期间给IC的集成带来了诸多挑战,其中等离子体诱导损伤(PID)是最具破坏性的一个。自多孔材料被发现以来,该行业已将重点从降低ILD的介电常数转移到克服这些集成挑战上。人们发明了更多的辅助前驱体(如Si-C-Si结构化合物)、沉积工艺(如NH等离子体处理)以及孔隙率后等离子体保护处理(P4)来解决与集成相关的挑战。在此,我们从以下三个方面介绍层间介电材料的发展历程,即介电材料的分类、沉积方法以及集成阶段遇到并解决的关键问题。我们旨在简要概述过去几十年来低k介电材料的发展情况。