Jung Woo-Jin, Park Jun-Young
School of Electronics Engineering, Chungbuk National University, Chungdae-ro 1, Chungbuk, Cheongju 28644, Korea.
Micromachines (Basel). 2021 Oct 22;12(11):1297. doi: 10.3390/mi12111297.
In contrast to conventional 2-dimensional (2D) NAND flash memory, in 3D NAND flash memory, cell-to-cell interference stemming from parasitic capacitance between the word-lines (WLs) is difficult to control because the number of WLs, achieved for better packing density, have been dramatically increased under limited height of NAND string. In this context, finding a novel approach based on dielectric engineering seems timely and applicable. This paper covers the voltage interference characteristics in 3D NAND with respect to dielectrics, then proposes an alternative cell structure to suppress such interference.
与传统的二维（2D）NAND闪存相比，在3D NAND闪存中，由于在NAND串有限的高度下为了实现更好的封装密度而大幅增加了字线（WL）的数量，字线之间寄生电容引起的单元间干扰难以控制。在这种情况下，寻找一种基于介电工程的新方法似乎是及时且适用的。本文涵盖了3D NAND中关于电介质的电压干扰特性，然后提出了一种替代单元结构来抑制这种干扰。
