• 文献检索
  • 文档翻译
  • 深度研究
  • 学术资讯
  • Suppr Zotero 插件Zotero 插件
  • 邀请有礼
  • 套餐&价格
  • 历史记录
应用&插件
Suppr Zotero 插件Zotero 插件浏览器插件Mac 客户端Windows 客户端微信小程序
定价
高级版会员购买积分包购买API积分包
服务
文献检索文档翻译深度研究API 文档MCP 服务
关于我们
关于 Suppr公司介绍联系我们用户协议隐私条款
关注我们

Suppr 超能文献

核心技术专利：CN118964589B侵权必究
粤ICP备2023148730 号-1Suppr @ 2026

文献检索

告别复杂PubMed语法，用中文像聊天一样搜索，搜遍4000万医学文献。AI智能推荐，让科研检索更轻松。

立即免费搜索

文件翻译

保留排版，准确专业，支持PDF/Word/PPT等文件格式，支持 12+语言互译。

免费翻译文档

深度研究

AI帮你快速写综述，25分钟生成高质量综述，智能提取关键信息，辅助科研写作。

立即免费体验

具有随机分布陷阱的3D垂直沟道NAND闪存中编程效率过冲的研究

Investigation of Program Efficiency Overshoot in 3D Vertical Channel NAND Flash with Randomly Distributed Traps.

作者信息

Park Chanyang, Yoon Jun-Sik, Nam Kihoon, Jang Hyundong, Park Minsang, Baek Rock-Hyun

机构信息

Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang 37673, Republic of Korea.

SK hynix Inc., Icheon 17336, Republic of Korea.

出版信息

Nanomaterials (Basel). 2023 Apr 24;13(9):1451. doi: 10.3390/nano13091451.

DOI:10.3390/nano13091451
PMID:37176997
原文链接:https://pmc.ncbi.nlm.nih.gov/articles/PMC10180439/
Abstract

The incremental step pulse programming slope (ISPP) with random variation was investigated by measuring numerous three-dimensional (3D) NAND flash memory cells with a vertical nanowire channel. We stored multiple bits in a cell with the ISPP scheme and read each cell pulse by pulse. The excessive tunneling from the channel to the storage layer determines the program efficiency overshoot. Then, a broadening of the threshold voltage distribution was observed due to the abnormal program cells. To analyze the randomly varying abnormal program behavior itself, we distinguished between the read variation and over-programming in measurements. Using a 3D Monte-Carlo simulation, which is a probabilistic approach to solve randomness, we clarified the physical origins of over-programming that strongly influence the abnormal program cells in program step voltage, and randomly distributed the trap site in the nitride of a nanoscale 3D NAND string. These causes have concurrent effects, but we divided and analyzed them quantitatively. Our results reveal the origins of the variation and the overshoot in the ISPP, widening the threshold voltage distribution with traps randomly located at the nanoscale. The findings can enhance understanding of random over-programming and help mitigate the most problematic programming obstacles for multiple-bit techniques.

摘要

通过测量众多具有垂直纳米线通道的三维（3D）NAND闪存单元，研究了具有随机变化的增量步脉冲编程斜率（ISPP）。我们采用ISPP方案在一个单元中存储多个比特，并逐脉冲读取每个单元。从通道到存储层的过度隧穿决定了编程效率过冲。然后，由于异常编程单元，观察到阈值电压分布变宽。为了分析随机变化的异常编程行为本身，我们在测量中区分了读取变化和过度编程。使用三维蒙特卡罗模拟（一种解决随机性的概率方法），我们阐明了过度编程的物理起源，其在编程步电压中强烈影响异常编程单元，并在纳米级3D NAND串的氮化物中随机分布陷阱位点。这些原因具有并发效应，但我们对其进行了定量划分和分析。我们的结果揭示了ISPP中变化和过冲的起源，拓宽了阈值电压分布，陷阱随机位于纳米尺度。这些发现可以增强对随机过度编程的理解，并有助于减轻多位技术中最具问题的编程障碍。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/39bd/10180439/da7d06f8c4c9/nanomaterials-13-01451-g008.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/39bd/10180439/5ab2ffe0ea16/nanomaterials-13-01451-g001.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/39bd/10180439/d3f02033bae6/nanomaterials-13-01451-g002.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/39bd/10180439/2970af92b4c4/nanomaterials-13-01451-g003.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/39bd/10180439/2ad8083cbdfc/nanomaterials-13-01451-g004.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/39bd/10180439/e4d6bb7ce9c4/nanomaterials-13-01451-g005.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/39bd/10180439/9cf6eafdb4a5/nanomaterials-13-01451-g006.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/39bd/10180439/bab2a41b7f98/nanomaterials-13-01451-g007.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/39bd/10180439/da7d06f8c4c9/nanomaterials-13-01451-g008.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/39bd/10180439/5ab2ffe0ea16/nanomaterials-13-01451-g001.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/39bd/10180439/d3f02033bae6/nanomaterials-13-01451-g002.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/39bd/10180439/2970af92b4c4/nanomaterials-13-01451-g003.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/39bd/10180439/2ad8083cbdfc/nanomaterials-13-01451-g004.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/39bd/10180439/e4d6bb7ce9c4/nanomaterials-13-01451-g005.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/39bd/10180439/9cf6eafdb4a5/nanomaterials-13-01451-g006.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/39bd/10180439/bab2a41b7f98/nanomaterials-13-01451-g007.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/39bd/10180439/da7d06f8c4c9/nanomaterials-13-01451-g008.jpg

相似文献

1
Investigation of Program Efficiency Overshoot in 3D Vertical Channel NAND Flash with Randomly Distributed Traps.具有随机分布陷阱的3D垂直沟道NAND闪存中编程效率过冲的研究
Nanomaterials (Basel). 2023 Apr 24;13(9):1451. doi: 10.3390/nano13091451.
2
Channel Modeling and Quantization Design for 3D NAND Flash Memory.用于3D NAND闪存的通道建模与量化设计
Entropy (Basel). 2023 Jun 21;25(7):965. doi: 10.3390/e25070965.
3
Impact of Stacking-Up and Scaling-Down Bit Cells in 3D NAND on Their Threshold Voltages.3D NAND中堆叠和缩减位单元对其阈值电压的影响。
Micromachines (Basel). 2022 Jul 18;13(7):1139. doi: 10.3390/mi13071139.
4
A Novel Channel Preparation Scheme to Optimize Program Disturbance in Three-Dimensional NAND Flash Memory.一种优化三维NAND闪存中编程干扰的新型通道制备方案。
Micromachines (Basel). 2024 Jan 31;15(2):223. doi: 10.3390/mi15020223.
5
Effects of the Grain Boundary and Interface Traps on the Electrical Characteristics of 3D NAND Flash Memory Devices.晶界和界面陷阱对3D NAND闪存器件电学特性的影响。
J Nanosci Nanotechnol. 2018 Mar 1;18(3):1944-1947. doi: 10.1166/jnn.2018.15000.
6
A Novel Program Scheme for Z-Interference Improvement in 3D NAND Flash Memory.一种用于改善3D NAND闪存中Z干扰的新型程序方案。
Micromachines (Basel). 2023 Apr 21;14(4):896. doi: 10.3390/mi14040896.
7
Optimal Energetic-Trap Distribution of Nano-Scaled Charge Trap Nitride for Wider Window in 3D NAND Flash Using a Machine-Learning Method.使用机器学习方法实现3D NAND闪存中更宽窗口的纳米级电荷陷阱氮化物的最佳能量陷阱分布
Nanomaterials (Basel). 2022 May 25;12(11):1808. doi: 10.3390/nano12111808.
8
Temperature Impacts on Endurance and Read Disturbs in Charge-Trap 3D NAND Flash Memories.温度对电荷陷阱式3D NAND闪存中耐久性和读取干扰的影响。
Micromachines (Basel). 2021 Sep 25;12(10):1152. doi: 10.3390/mi12101152.
9
Dielectric Engineering to Suppress Cell-to-Cell Programming Voltage Interference in 3D NAND Flash Memory.用于抑制3D NAND闪存中单元间编程电压干扰的介电工程
Micromachines (Basel). 2021 Oct 22;12(11):1297. doi: 10.3390/mi12111297.
10
Adaptive Bitline Voltage Countermeasure for Neighbor Wordline Interference in 3D NAND Flash Memory-Based Sensors.基于 3D NAND 闪存传感器的自适应位线电压对策，用于缓解邻位线干扰。
Sensors (Basel). 2023 Mar 17;23(6):3212. doi: 10.3390/s23063212.

引用本文的文献

1
Ferroelectric NAND for efficient hardware bayesian neural networks.用于高效硬件贝叶斯神经网络的铁电与非门
Nat Commun. 2025 Jul 25;16(1):6879. doi: 10.1038/s41467-025-61980-y.