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IEEE Trans Biomed Circuits Syst. 2019 Dec;13(6):1714-1722. doi: 10.1109/TBCAS.2019.2947130. Epub 2019 Oct 14.
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Feature extraction using extrema sampling of discrete derivatives for spike sorting in implantable upper-limb neural prostheses.用于可植入上肢神经假体中尖峰分类的离散导数极值采样特征提取
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High-performance neuroprosthetic control by an individual with tetraplegia.高位截瘫患者的高性能神经假体控制。
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迈向体内神经解码。

Towards in vivo neural decoding.

作者信息

Valencia Daniel, Alimohammad Amir

机构信息

Department of Electrical and Computer Engineering, San Diego State University, San Diego, USA.

出版信息

Biomed Eng Lett. 2022 Feb 10;12(2):185-195. doi: 10.1007/s13534-022-00217-z. eCollection 2022 May.

DOI:10.1007/s13534-022-00217-z
PMID:35529345
原文链接:https://pmc.ncbi.nlm.nih.gov/articles/PMC9046500/
Abstract

Conventional spike sorting and motor intention decoding algorithms are mostly implemented on an external computing device, such as a personal computer. The innovation of high-resolution and high-density electrodes to record the brain's activity at the single neuron level may eliminate the need for spike sorting altogether while potentially enabling in vivo neural decoding. This article explores the feasibility and efficient realization of in vivo decoding, with and without spike sorting. The efficiency of neural network-based models for reliable motor decoding is presented and the performance of candidate neural decoding schemes on sorted single-unit activity and unsorted multi-unit activity are evaluated. A programmable processor with a custom instruction set architecture, for the first time to the best of our knowledge, is designed and implemented for executing neural network operations in a standard 180-nm CMOS process. The processor's layout is estimated to occupy 49 mm of silicon area and to dissipate 12 mW of power from a 1.8 V supply, which is within the tissue-safe operation of the brain.

摘要

传统的尖峰排序和运动意图解码算法大多在外部计算设备(如个人计算机)上实现。用于在单神经元水平记录大脑活动的高分辨率和高密度电极的创新可能完全消除对尖峰排序的需求,同时有可能实现体内神经解码。本文探讨了有无尖峰排序情况下体内解码的可行性和高效实现方式。展示了基于神经网络的模型用于可靠运动解码的效率,并评估了候选神经解码方案对已排序单单元活动和未排序多单元活动的性能。据我们所知,首次设计并实现了一种具有定制指令集架构的可编程处理器,用于在标准180纳米CMOS工艺中执行神经网络操作。该处理器的版图估计占据49平方毫米的硅面积,从1.8伏电源消耗12毫瓦的功率,这在大脑组织安全操作范围内。