IEEE Trans Neural Syst Rehabil Eng. 2021;29:206-214. doi: 10.1109/TNSRE.2020.3043403. Epub 2021 Mar 1.
This article presents the design and efficient hardware implementation of binarized neural networks (BNNs) for brain-implantable neural spike sorting. In contrast to the conventional artificial neural networks (ANNs), in which the weights and activation functions of neurons are represented using real values, the BNNs utilize binarized weights and activation functions to dramatically reduce the memory requirement and computational complexity of the ANNs. The designed BNN is trained using several realistic neural datasets to verify its accuracy for neural spike sorting. The application-specific integrated circuit (ASIC) implementation of the designed BNN in a standard 0.18- [Formula: see text] CMOS process occupies 0.33 mm of silicon area. Power consumption estimation of the ASIC layout shows that the BNN dissipates [Formula: see text] of power from a 1.8 V supply while operating at 24 kHz. The designed BNN-based spike sorting system is also implemented on a field-programmable gate array and is shown to reduce the required on-chip memory by 89% compared to those of the alternative state-of-the-art spike sorting systems. To the best of our knowledge, this is the first work employing BNNs for real-time in vivo neural spike sorting.
本文提出了用于脑植入神经尖峰分类的二进制神经网络 (BNN) 的设计和高效硬件实现。与传统的人工神经网络 (ANN) 不同，神经元的权重和激活函数在 BNN 中使用二进制数表示，从而大大降低了 ANN 的内存需求和计算复杂度。所设计的 BNN 使用几个现实的神经数据集进行训练，以验证其用于神经尖峰分类的准确性。所设计的 BNN 在标准 0.18-µm CMOS 工艺中的专用集成电路 (ASIC) 实现占用 0.33 mm² 的硅面积。ASIC 布局的功耗估计表明，BNN 在 24 kHz 时从 1.8 V 电源消耗[Formula: see text]的功率。所设计的基于 BNN 的尖峰分类系统也在现场可编程门阵列上实现，并与其他最先进的尖峰分类系统相比，显示出所需的片上内存减少了 89%。据我们所知，这是首次将 BNN 用于实时体内神经尖峰分类的工作。
