Lim Namsoo, Yoo Tae Jin, Kim Jin Tae, Pak Yusin, Kumaresan Yogeenth, Kim Hyeonghun, Kim Woochul, Lee Byoung Hun, Jung Gun Young
School of Materials Science and Engineering, Gwangju Institute of Science and Technology (GIST) Gwangju 500-712 Republic of Korea
Creative Future Research Laboratory, Electronics and Telecommunications Research Institute 218, Gajeong-ro Yuseong Daejeon 305-700 Republic of Korea.
RSC Adv. 2018 Feb 28;8(17):9031-9037. doi: 10.1039/c7ra11601b.
A tunable graphene doping method utilizing a SiO/Si substrate with nanopores (NP) was introduced. Laser interference lithography (LIL) using a He-Cd laser ( = 325 nm) was used to prepare pore size- and pitch-controllable NP SiO/Si substrates. Then, bottom-contact graphene field effect transistors (G-FETs) were fabricated on the NP SiO/Si substrate to measure the transfer curves. The graphene transferred onto the NP SiO/Si substrate showed relatively n-doped behavior compared to the graphene transferred onto a flat SiO/Si substrate, as evidenced by the blue-shift of the 2D peak position (∼2700 cm) in the Raman spectra due to contact doping. As the porosity increased within the substrate, the Dirac voltage shifted to a more positive or negative value, depending on the initial doping type (p- or n-type, respectively) of the contact doping. The Dirac voltage shifts with porosity were ascribed mainly to the compensation for the reduced capacitance owing to the SiO-air hetero-structured dielectric layer within the periodically aligned nanopores capped by the suspended graphene (electrostatic doping). The hysteresis (Dirac voltage difference during the forward and backward scans) was reduced when utilizing an NP SiO/Si substrate with smaller pores and/or a low porosity because fewer HO or O molecules could be trapped inside the smaller pores.
介绍了一种利用具有纳米孔(NP)的SiO/Si衬底的可调谐石墨烯掺杂方法。使用氦镉激光器(λ = 325 nm)的激光干涉光刻(LIL)来制备孔径和间距可控的NP SiO/Si衬底。然后,在NP SiO/Si衬底上制造底部接触式石墨烯场效应晶体管(G-FET)以测量转移曲线。转移到NP SiO/Si衬底上的石墨烯与转移到平坦SiO/Si衬底上的石墨烯相比表现出相对的n型掺杂行为,这通过拉曼光谱中由于接触掺杂导致的2D峰位置(~2700 cm)的蓝移得到证明。随着衬底内孔隙率的增加,狄拉克电压根据接触掺杂的初始掺杂类型(分别为p型或n型)向更正或更负的值移动。狄拉克电压随孔隙率的变化主要归因于对由悬浮石墨烯覆盖的周期性排列的纳米孔内的SiO-空气异质结构介电层导致的电容减小的补偿(静电掺杂)。当使用具有较小孔和/或低孔隙率的NP SiO/Si衬底时,滞后现象(正向和反向扫描期间的狄拉克电压差)会减小,因为较少的HO或O分子可以被困在较小的孔内。