Sridhar Nagisetty, Senthilpari C, Mardeni R, Yong Wong Hin, Nandhakumar T
Faculty of Engineering, Multimedia University (MMU), Cyberjaya, Malaysia.
Nottingham University (Malaysia Campus), Semenyih, Malaysia.
Sci Rep. 2022 May 16;12(1):8101. doi: 10.1038/s41598-022-12235-z.
In wireless communication networks, the necessity for high-speed data rates has increased in emerging 5G application areas. The Power Amplifier (PA) topologies reported to date achieved desired Power Added Efficiency (PAE) and linearity. However, these harmonically tuned switching PAs are less appealing for broadband applications as they are restricted to narrow bandwidth (BW). Therefore, to meet the 5G requirements, the challenge of designing a PA with improved efficiency and linearity for a dynamic range of BW becomes critical for PA designers. Recently developed Class-J PA topology can obtain good efficiency while maintaining linearity for wide BW applications. This research work presents a methodology to design a 5 GHz Class-J mode PA topology using Silterra 0.13 μm CMOS technology. This research's main objectives are to determine the R of the transistor and design a proper Output Matching Network (OMN) for obtaining Class-J PA operation to make it suitable for 5G wireless applications. The simulation results represent that the designed Class-J PA provides 27 dBm of maximum power output with a maximum power gain of 13.7 dB and the small-signal gain of 17 dB for a BW of around 500 MHz with a 5 V power supply into a 50Ω load.
在无线通信网络中，新兴的5G应用领域对高速数据速率的需求不断增加。迄今为止报道的功率放大器（PA）拓扑结构实现了所需的功率附加效率（PAE）和线性度。然而，这些谐波调谐开关PA对于宽带应用吸引力较小，因为它们限于窄带宽（BW）。因此，为满足5G要求，为动态范围的带宽设计具有更高效率和线性度的PA对PA设计者而言成为关键挑战。最近开发的J类PA拓扑结构在保持宽带宽应用线性度的同时可获得良好的效率。本研究工作提出了一种使用Silterra 0.13μm CMOS技术设计5GHz J类模式PA拓扑结构的方法。本研究的主要目标是确定晶体管的R并设计合适的输出匹配网络（OMN）以实现J类PA操作，使其适用于5G无线应用。仿真结果表明，所设计的J类PA在5V电源输入50Ω负载的情况下，对于约500MHz的带宽，可提供27dBm的最大功率输出，最大功率增益为13.7dB，小信号增益为17dB。
