Dang Weiqi, Lu Zheyi, Zhao Bei, Li Bo, Li Jia, Zhang Hongmei, Song Rong, Hossain Mongur, Le Zhikai, Liu Yuan, Duan Xidong
Hunan Key Laboratory of Two-Dimensional Materials and State Key Laboratory for Chemo/Biosensing and Chemometrics, College of Chemistry and Chemical Engineering, Hunan University, Changsha 410082, People's Republic of China.
Hunan Key Laboratory of Two-Dimensional Materials, Department of Applied Physics, School of Physics and Electronics, Hunan University, Changsha 410082, People's Republic of China.
Nanotechnology. 2022 Jul 4;33(39). doi: 10.1088/1361-6528/ac76d4.
The increase of gate leakage current when the gate dielectric layer is thinned is a key issue for device scalability. For scaling down the integrated circuits, a thin gate dielectric layer with a low leakage current is essential. Currently, changing the dielectric layer material or enhancing the surface contact between the gate dielectric and the channel material is the most common way to reduce gate leakage current in devices. Herein, we report a technique of enhancing the surface contact between the gate dielectric and the metal electrode, that is constructing an Au/AlO/Si metal-oxide-semiconductor device by replacing the typical evaporated electrode/dielectric layer contact with a transferred electrode/high-dielectric layer contact. The contact with a mild, non-invasive interface can ensure the intrinsic insulation of the dielectric layer. By applying 2-40 nm AlOas the dielectric layer, the current density-electrical field (-) measurement reveals that the dielectric leakage generated by the transferred electrode is less than that obtained by the typical evaporated electrode with a ratio of 0.3 × 10 ∼ 5 × 10at = 1 V. Furthermore, at = 1 mA cm, the withstand voltage can be raised by 10-10times over that of an evaporated electrode. The capacitance-voltage (-) test shows that the transferred metal electrode can efficiently scale the equivalent oxide layer thickness (EOT) to 1.58 nm, which is a relatively smaller value than the overall reported Si-based device's EOT. This finding successfully illustrates that the transferred electrode/dielectric layer's mild contact can balance the scaling of the gate dielectric layer with a minimal leakage current and constantly reduce the EOT. Our enhanced electrode/dielectric contact approach provides a straightforward and effective pathway for further scaling of devices in integrated circuits and significantly decreases the overall integrated circuit's static power consumption (ICs).
当栅极介电层变薄时，栅极漏电流的增加是器件可扩展性的关键问题。为了缩小集成电路尺寸，具有低漏电流的薄栅极介电层至关重要。目前，改变介电层材料或增强栅极介电层与沟道材料之间的表面接触是降低器件栅极漏电流最常用的方法。在此，我们报道了一种增强栅极介电层与金属电极之间表面接触的技术，即通过用转移电极/高介电常数层接触取代典型的蒸发电极/介电层接触来构建Au/AlO/Si金属氧化物半导体器件。具有温和、非侵入性界面的接触可以确保介电层的本征绝缘性。通过施加2 - 40 nm的AlO作为介电层，电流密度 - 电场（J - E）测量表明，转移电极产生的介电漏电小于典型蒸发电极在V = 1 V时的介电漏电，其比例为0.3×10⁻⁶～5×10⁻⁶。此外，在J = 1 mA/cm²时，耐压比蒸发电极提高了10 - 100倍。电容 - 电压（C - V）测试表明，转移金属电极可以有效地将等效氧化层厚度（EOT）缩小到1.58 nm，这是一个比总体报道的基于Si的器件的EOT相对更小的值。这一发现成功地表明，转移电极/介电层的温和接触可以在最小漏电流的情况下平衡栅极介电层的缩小，并持续降低EOT。我们增强的电极/介电接触方法为集成电路中器件的进一步缩小提供了一条直接有效的途径，并显著降低了整个集成电路的静态功耗（ICs）。
