Jiang Yifan, Shen Rui, Li Tong, Tian Jiamin, Li Shuo, Tan Hark Hoe, Jagadish Chennupati, Chen Qing
Key Laboratory for the Physic and Chemistry of Nanodevices, School of Electronics, Peking University, Beijing 100871, China.
Department of Electronic Materials Engineering, ARC Centre of Excellence for Transformative Meta-Optical Systems, Research School of Physics, The Australian National University, Canberra, ACT 2601, Australia.
Nanoscale. 2022 Sep 15;14(35):12830-12840. doi: 10.1039/d2nr02736d.
Due to their excellent electrical characteristics, InAs nanowires (NWs) have great potential as conducting channels in integrated circuits. However, the surface effect and loose native oxide coverage can deteriorate the performance of InAs NW transistors. YO, a high- dielectric with low Gibbs free energy, has been proposed to modify the InAs NW surface. Here, we systematically investigate the effect of YO coating on the performance of InAs NW field-effect transistors (FETs). We first explore the influence of the thermal oxidation process of YO on the performance of back-gated FETs. We then observe that the coverage of YO/HfO bilayers on the NW decreases the hysteresis (the smallest value reaches 0.1 V), subthreshold swing (SS, down to 169 mV dec) and on-state resistance , and increases the field-effect mobility (up to 4876.1 cm V s) and the on-off ratio, mainly owing to the passivation effect on the NW surface. Finally, paired top-gated NW FETs with a YO/HfO bilayer and a single layer of HfO dielectric are fabricated and compared. The YO/HfO bilayer provides better gate control (SS = 113 mV dec) under a smaller gate oxide capacitance, with an interface trap density as low as 1.93 × 10 eV cm. The use of the YO/HfO stack provides an effective strategy to enhance the performance of III-V-based transistors for future applications.
由于具有出色的电学特性，砷化铟纳米线（NWs）在集成电路中作为导电通道具有巨大潜力。然而，表面效应和疏松的原生氧化物覆盖会使砷化铟NW晶体管的性能恶化。有人提出用氧化钇（YO）这种具有低吉布斯自由能的高介电常数材料来修饰砷化铟NW表面。在此，我们系统地研究了YO涂层对砷化铟NW场效应晶体管（FETs）性能的影响。我们首先探究YO的热氧化过程对背栅FET性能的影响。然后我们观察到NW上YO/HfO双层膜的覆盖降低了滞后现象（最小值达到0.1 V）、亚阈值摆幅（SS，低至169 mV/dec）和导通电阻，并提高了场效应迁移率（高达4876.1 cm²/V·s）以及开/关比，这主要归因于对NW表面的钝化作用。最后，制备并比较了具有YO/HfO双层膜和单层HfO电介质的成对顶栅NW FET。YO/HfO双层膜在较小的栅极氧化物电容下提供了更好的栅极控制（SS = 113 mV/dec），界面陷阱密度低至1.93×10¹² eV/cm²。使用YO/HfO堆叠结构为增强未来应用中基于III - V族的晶体管性能提供了一种有效策略。
