Enhancing the electrical performance of InAs nanowire field-effect transistors by improving the surface and interface properties by coating with thermally oxidized YO.

Due to their excellent electrical characteristics, InAs nanowires (NWs) have great potential as conducting channels in integrated circuits. However, the surface effect and loose native oxide coverage can deteriorate the performance of InAs NW transistors. YO, a high- dielectric with low Gibbs free energy, has been proposed to modify the InAs NW surface. Here, we systematically investigate the effect of YO coating on the performance of InAs NW field-effect transistors (FETs). We first explore the influence of the thermal oxidation process of YO on the performance of back-gated FETs. We then observe that the coverage of YO/HfO bilayers on the NW decreases the hysteresis (the smallest value reaches 0.1 V), subthreshold swing (SS, down to 169 mV dec) and on-state resistance , and increases the field-effect mobility (up to 4876.1 cm V s) and the on-off ratio, mainly owing to the passivation effect on the NW surface. Finally, paired top-gated NW FETs with a YO/HfO bilayer and a single layer of HfO dielectric are fabricated and compared. The YO/HfO bilayer provides better gate control (SS = 113 mV dec) under a smaller gate oxide capacitance, with an interface trap density as low as 1.93 × 10 eV cm. The use of the YO/HfO stack provides an effective strategy to enhance the performance of III-V-based transistors for future applications.