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在铁电 Al 掺杂 HfO/ HfO 栅介质堆叠中通过负电容效应改善 MoS 晶体管的亚阈值摆幅。

Subthreshold swing improvement in MoS transistors by the negative-capacitance effect in a ferroelectric Al-doped-HfO/HfO gate dielectric stack.

机构信息

Department of Electrical Engineering and Computer Sciences, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139, USA.

出版信息

Nanoscale. 2017 May 11;9(18):6122-6127. doi: 10.1039/c7nr00088j.

Abstract

Obtaining a subthreshold swing (SS) below the thermionic limit of 60 mV dec by exploiting the negative-capacitance (NC) effect in ferroelectric (FE) materials is a novel effective technique to allow the reduction of the supply voltage and power consumption in field effect transistors (FETs). At the same time, two-dimensional layered semiconductors, such as molybdenum disulfide (MoS), have been shown to be promising candidates to replace silicon MOSFETs in sub-5 nm-channel technology nodes. In this paper, we demonstrate NC MoS FETs by incorporating a ferroelectric Al-doped HfO (Al : HfO), a technologically compatible material, in the FET gate stack. Al : HfO thin films were deposited on Si wafers by atomic layer deposition. Voltage amplification up to 1.25 times was observed in a FE bilayer stack of Al : HfO/HfO with a Ni metallic intermediate layer. The minimum SS (SS) of the NC-MoS FET built on the FE bilayer improved to 57 mV dec at room temperature, compared with SS = 67 mV dec for the MoS FET with only HfO as a gate dielectric.

摘要

通过利用铁电 (FE) 材料中的负电容 (NC) 效应获得低于热离子极限 60 mV/dec 的亚阈值摆幅 (SS),是一种允许降低场效应晶体管 (FET) 中电源电压和功耗的新有效技术。同时,二维层状半导体,如二硫化钼 (MoS),已被证明是在亚 5nm 沟道技术节点中替代硅 MOSFET 的有前途的候选材料。在本文中,我们通过在 FET 栅极堆叠中引入铁电掺铝的 HfO (Al:HfO),一种技术上兼容的材料,来展示 NC MoS FET。通过原子层沉积在 Si 晶圆上沉积 Al:HfO 薄膜。在具有 Ni 金属中间层的 Al:HfO/HfO 铁电双层堆叠中观察到 1.25 倍的电压放大。与仅使用 HfO 作为栅介质的 MoS FET 的 SS = 67 mV/dec 相比,构建在 FE 双层上的 NC-MoS FET 的最小 SS (SS) 改善至 57 mV/dec,室温下。

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