Department of Materials Science and Engineering, The University of Texas at Dallas , 800 W Campbell Rd., Richardson, Texas 75080, United States.
Tyndall National Institute, Department of Chemistry, University of College Cork , Lee Maltings, Dyke Parade, Cork, Ireland.
ACS Appl Mater Interfaces. 2017 Jul 19;9(28):24348-24356. doi: 10.1021/acsami.7b06204. Epub 2017 Jul 6.
The electronic properties of the HfO/MoS interface were investigated using multifrequency capacitance-voltage (C-V) and current-voltage characterization of top-gated MoS metal-oxide-semiconductor field effect transistors (MOSFETs). The analysis was performed on few layer (5-10) MoS MOSFETs fabricated using photolithographic patterning with 13 and 8 nm HfO gate oxide layers formed by atomic layer deposition after in-situ UV-O surface functionalization. The impedance response of the HfO/MoS gate stack indicates the existence of specific defects at the interface, which exhibited either a frequency-dependent distortion similar to conventional Si MOSFETs with unpassivated silicon dangling bonds or a frequency dispersion over the entire voltage range corresponding to depletion of the HfO/MoS surface, consistent with interface traps distributed over a range of energy levels. The interface defects density (D) was extracted from the C-V responses by the high-low frequency and the multiple-frequency extraction methods, where a D peak value of 1.2 × 10 cm eV was extracted for a device (7-layer MoS and 13 nm HfO) exhibiting a behavior approximating to a single trap response. The MoS MOSFET with 4-layer MoS and 8 nm HfO gave D values ranging from 2 × 10 to 2 × 10 cm eV across the energy range corresponding to depletion near the HfO/MoS interface. The gate current was below 10 A/cm across the full bias sweep for both samples indicating continuous HfO films resulting from the combined UV ozone and HfO deposition process. The results demonstrated that impedance spectroscopy applied to relatively simple top-gated transistor test structures provides an approach to investigate electrically active defects at the HfO/MoS interface and should be applicable to alternative TMD materials, surface treatments, and gate oxides as an interface defect metrology tool in the development of TMD-based MOSFETs.
采用顶部栅极 MoS 金属氧化物半导体场效应晶体管 (MOSFET) 的多频电容-电压 (C-V) 和电流-电压特性对 HfO/MoS 界面的电子特性进行了研究。该分析是在使用光刻图案化制造的少数层 (5-10) MoS MOSFET 上进行的,使用原子层沉积 (ALD) 在原位 UV-O 表面功能化后形成的 13nm 和 8nm HfO 栅极氧化物层。HfO/MoS 栅堆叠的阻抗响应表明界面处存在特定缺陷,这些缺陷表现为具有未钝化硅悬挂键的传统 Si MOSFET 类似的频率相关失真,或者在整个电压范围内表现出与 HfO/MoS 表面耗尽对应的频率色散,与分布在一系列能级上的界面陷阱一致。界面缺陷密度 (D) 通过高低频和多频提取方法从 C-V 响应中提取,其中一个器件(7 层 MoS 和 13nm HfO)表现出类似于单个陷阱响应的行为,提取出 D 峰值为 1.2×10 cm eV。对于具有 4 层 MoS 和 8nm HfO 的 MoS MOSFET,在对应于 HfO/MoS 界面附近耗尽的能量范围内,D 值范围为 2×10 到 2×10 cm eV。两个样品的栅极电流在整个偏置扫描范围内均低于 10 A/cm,表明在结合 UV 臭氧和 HfO 沉积工艺后形成了连续的 HfO 薄膜。结果表明,应用于相对简单的顶部栅极晶体管测试结构的阻抗谱提供了一种研究 HfO/MoS 界面上电活性缺陷的方法,并且应该适用于替代 TMD 材料、表面处理和栅极氧化物,作为 TMD 基 MOSFET 开发中的界面缺陷计量工具。