Large Dense Periodic Arrays of Vertically Aligned Sharp Silicon Nanocones.

Convex cylindrical silicon nanostructures, also referred to as silicon nanocones, find their value in many applications ranging from photovoltaics to nanofluidics, nanophotonics, and nanoelectronic applications. To fabricate silicon nanocones, both bottom-up and top-down methods can be used. The top-down method presented in this work relies on pre-shaping of silicon nanowires by ion beam etching followed by self-limited thermal oxidation. The combination of pre-shaping and oxidation obtains high-density, high aspect ratio, periodic, and vertically aligned sharp single-crystalline silicon nanocones at the wafer-scale. The homogeneity of the presented nanocones is unprecedented and may give rise to applications where numerical modeling and experiments are combined without assumptions about morphology of the nanocone. The silicon nanocones are organized in a square periodic lattice, with 250 nm pitch giving arrays containing 1.6 billion structures per square centimeter. The nanocone arrays were several mm in size and located centimeters apart across a 100-mm-diameter single-crystalline silicon (100) substrate. For single nanocones, tip radii of curvature < 3 nm were measured. The silicon nanocones were vertically aligned, baring a height variation of < 5 nm (< 1%) for seven adjacent nanocones, whereas the height inhomogeneity is < 80 nm (< 16%) across the full wafer scale. The height inhomogeneity can be explained by inhomogeneity present in the radii of the initial columnar polymer mask. The presented method might also be applicable to silicon micro- and nanowires derived through other top-down or bottom-up methods because of the combination of ion beam etching pre-shaping and thermal oxidation sharpening. A novel method is presented where argon ion beam etching and thermal oxidation sharpening are combined to tailor a high-density single-crystalline silicon nanowire array into a vertically aligned single-crystalline silicon nanocones array with < 3 nm apex radius of curvature tips, at the wafer scale.