Lee Taegoon, Jeon Seung-Bae, Kim Daewon
Department of Electronic Engineering, Kyung Hee University, 1732 Deogyeong-daero, Giheung-gu, Yongin 17104, Korea.
Department of Electronic Engineering, Hanbat National University, 125 Dongseo-daero, Yuseong-gu, Daejeon 34158, Korea.
Micromachines (Basel). 2022 Oct 14;13(10):1740. doi: 10.3390/mi13101740.
A novel inhibitable and firing threshold voltage tunable vertical nanowire (NW) single transistor neuron device with core-shell dual-gate (CSDG) was realized and verified by TCAD simulation. The CSDG NW neuron is enclosed by an independently accessed shell gate and core gate to serve an excitatory-inhibitory transition and a firing threshold voltage adjustment, respectively. By utilizing the shell gate, the firing of specific neuron can be inhibited for winner-takes-all learning. It was confirmed that the independently accessed core gate can be used for adjustment of the firing threshold voltage to compensate random conductance variation before the learning and to fix inference error caused by unwanted synapse conductance change after the learning. This threshold voltage tuning can also be utilized for homeostatic function during the learning process. Furthermore, a myelination function which controls the transmission rate was obtained based on the inherent asymmetry between the source and drain in vertical NW structure. Finally, using the CSDG NW neuron device, a letter recognition test was conducted by SPICE simulation for a system-level validation. This multi-functional neuron device can contribute to construct a high-density monolithic SNN hardware combining with the previously developed vertical synapse MOSFET devices.
通过TCAD模拟实现并验证了一种新型的具有抑制功能且发射阈值电压可调的垂直纳米线（NW）单晶体管神经元器件，该器件采用了核壳双栅（CSDG）结构。CSDG NW神经元由独立控制的壳栅和核栅包围，分别用于实现兴奋-抑制转换和发射阈值电压调节。通过利用壳栅，可以抑制特定神经元的放电，以实现胜者全得学习。已证实，独立控制的核栅可用于调节发射阈值电压，以补偿学习前的随机电导变化，并修正学习后由不必要的突触电导变化引起的推理误差。这种阈值电压调节也可在学习过程中用于稳态功能。此外，基于垂直NW结构中源极和漏极之间固有的不对称性，获得了控制传输速率的髓鞘形成功能。最后，使用CSDG NW神经元器件，通过SPICE模拟进行了字母识别测试，以进行系统级验证。这种多功能神经元器件有助于与先前开发的垂直突触MOSFET器件相结合，构建高密度单片SNN硬件。
