Zhao Dongxue, Xia Zhiliang, Yang Tao, Yang Yuancheng, Zhou Wenxi, Huo Zongliang
Institute of the Microelectronics of Chinese Academy of Sciences, Beijing 100029, China.
University of Chinese Academy of Sciences, Beijing 100049, China.
Micromachines (Basel). 2022 Oct 19;13(10):1772. doi: 10.3390/mi13101772.
A novel vertical dual surrounding gate transistor with embedded oxide layer is proposed for capacitorless single transistor DRAM (1T DRAM). The embedded oxide layer is innovatively used to improve the retention time by reducing the recombination rate of stored holes and sensing electrons. Based on TCAD simulations, the new structure is predicted to not only have the characteristics of fast access, random read and integration of 4F cell, but also to realize good retention and deep scaling. At the same time, the new structure has the potential of scaling compared with the conventional capacitorless 1T DRAM.
本文提出了一种用于无电容单晶体管动态随机存取存储器(1T DRAM)的新型垂直双环绕栅晶体管,其带有嵌入式氧化层。该嵌入式氧化层通过降低存储空穴与传感电子的复合率,创新性地用于提高数据保持时间。基于TCAD模拟,预测这种新结构不仅具有快速访问、随机读取以及4F单元集成的特性,还能实现良好的数据保持性能和深度缩放。同时,与传统的无电容1T DRAM相比,这种新结构具有缩放的潜力。