Charge Trapping and Emission Properties in CAAC-IGZO Transistor: A First-Principles Calculations.

The c-axis aligned crystalline indium-gallium-zinc-oxide field-effect transistor (CAAC-IGZO FET), exhibiting an extremely low off-state leakage current (10 A/μm), has promised to be an ideal candidate for Dynamic Random Access Memory (DRAM) applications. However, the instabilities leaded by the drift of the threshold voltage in various stress seriously affect the device application. To better develop high performance CAAC-IGZO FET for DRAM applications, it's essential to uncover the deep physical process of charge transport mechanism in CAAC-IGZO FET. In this work, by combining the first-principles calculations and nonradiative multiphonon theory, the charge trapping and emission properties in CAAC-IGZO FET have been systematically investigated. It is found that under positive bias stress, hydrogen interstitial in AlO gate dielectric is probable effective electron trap center, which has the transition level (ε (+1/-1) = 0.52 eV) above Fermi level. But it has a high capture barrier about 1.4 eV and low capture rate. Under negative bias stress, oxygen vacancy in AlO gate dielectric and CAAC-IGZO active layer are probable effective electron emission centers whose transition level ε (+2/0) distributed at -0.73-0.98 eV and 0.69 eV below Fermi level. They have a relatively low emission barrier of about 0.5 eV and 0.25 eV and high emission rate. To overcome the instability in CAAC-IGZO FET, some approaches can be taken to control the hydrogen concentration in AlO dielectric layer and the concentration of the oxygen vacancy. This work can help to understand the mechanisms of instability of CAAC-IGZO transistor caused by the charge capture/emission process.