Langpoklakpam Catherine, Liu An-Chen, You Neng-Jie, Kao Ming-Hsuan, Huang Wen-Hsien, Shen Chang-Hong, Tzou Jerry, Kuo Hao-Chung, Shieh Jia-Min
Department of Photonics, Institute of Electro-Optical Engineering, College of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu 30010, Taiwan.
Taiwan Semiconductor Research Institute (TSRI), Hsinchu 30078, Taiwan.
Micromachines (Basel). 2023 Feb 28;14(3):576. doi: 10.3390/mi14030576.
In this study, we report a low ohmic contact resistance process on a 650 V E-mode p-GaN gate HEMT structure. An amorphous silicon (a-Si) assisted layer was inserted in between the ohmic contact and GaN. The fabricated device exhibits a lower contact resistance of about 0.6 Ω-mm after annealing at 550 °C. In addition, the threshold voltage shifting of the device was reduced from -0.85 V to -0.74 V after applying a high gate bias stress at 150 °C for 10 s. The measured time to failure (TTF) of the device shows that a low thermal budget process can improve the device's reliability. A 100-fold improvement in HTGB TTF was clearly demonstrated. The study shows a viable method for CMOS-compatible GaN power device fabrication.
在本研究中，我们报告了一种在650 V E模式p型氮化镓栅极高电子迁移率晶体管（HEMT）结构上实现低欧姆接触电阻的工艺。在欧姆接触和氮化镓之间插入了非晶硅（a-Si）辅助层。制造的器件在550°C退火后表现出约0.6Ω·mm的较低接触电阻。此外，在150°C下施加10 s的高栅极偏置应力后，器件的阈值电压偏移从-0.85 V降低到-0.74 V。器件的测量失效时间（TTF）表明，低热预算工艺可以提高器件的可靠性。明显证明了高温栅极偏置（HTGB）TTF提高了100倍。该研究展示了一种用于与CMOS兼容的氮化镓功率器件制造的可行方法。
