Additive 3D photonic integration that is CMOS compatible.

Today, continued miniaturization in electronic integrated circuits (ICs) appears to have reached its fundamental limit at ∼2 nm feature-sizes, from originally ∼1 cm. At the same time, energy consumption due to communication becomes the dominant limitation in high performance electronic ICs for computing, and modern computing concepts such neural networks further amplify the challenge. Communication based on co-integrated photonic circuits is a promising strategy to address the second. As feature size has leveled out, adding a third dimension to the predominantly two-dimensional ICs appears a promising future strategy for further IC architecture improvement. Crucial for efficient electronic-photonic co-integration is complementary metal-oxide-semiconductor (CMOS) compatibility of the associated photonic integration fabrication process. Here, we review our latest results obtained in the FEMTO-ST RENATECH facilities on using additive photo-induced polymerization of a standard photo-resin for truly three-dimensional (3D) photonic integration according to these principles. Based on one- and two-photon polymerization (TPP) and combined with direct-laser writing, we 3D-printed air- and polymer-cladded photonic waveguides. An important application of such circuits are the interconnects of optical neural networks, where 3D integration enables scalability in terms of network size versus its geometric dimensions. In particular via-TPP, a fabrication process combining blanket one- and high-resolution TPP, we demonstrated polymer-cladded step-index waveguides with up to 6 mm length, low insertion (∼0.26 dB) and propagation (∼1.3 dB mm) losses, realized broadband and low loss (∼0.06 dB splitting losses) adiabatic 1 to M couplers as well as tightly confining air-cladded waveguides for denser integration. By stably printing such integrated photonic circuits on standard semiconductor samples, we show the concept's CMOS compatibility. With this, we lay out a promising, future avenue for scalable integration of hybrid photonic and electronic components.