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基于不同指令集架构的软核处理器集成以及现场可编程门阵列定制数据路径实现。

Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation.

作者信息

Zagan Ionel, Găitan Vasile Gheorghiţă

机构信息

Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University, Suceava, Romania.

Integrated Center for Research, Development and Innovation in Advanced Materials, Nanotechnologies, and Distributed Systems for Fabrication and Control (MANSiD), Stefan cel Mare University, Suceava, Romania.

出版信息

PeerJ Comput Sci. 2023 Apr 18;9:e1300. doi: 10.7717/peerj-cs.1300. eCollection 2023.

DOI:10.7717/peerj-cs.1300
PMID:37346607
原文链接:https://pmc.ncbi.nlm.nih.gov/articles/PMC10280498/
Abstract

One of the fundamental requirements of a real-time system (RTS) is the need to guarantee re-al-time determinism for critical tasks. Task execution rates, operating system (OS) overhead, and task context switching times are just a few of the parameters that can cause jitter and missed deadlines in RTS with soft schedulers. Control systems that are susceptible to jitter can be used in the control of HARD RTS as long as the cumulative value of periodicity deviation and worst-case response time is less than the response time required by that application. This artcle presents field-programmable gate array (FPGA) soft-core processors integration based on different instruction set architectures (ISA), custom central processing unit (CPU) datapath, dedicated hardware thread context, and hardware real-time operating system (RTOS) implementations. Based on existing work problems, one parameter that can negatively influence the performance of an RTS is the additional costs due to the operating system. The scheduling and thread context switching operations can significantly degrade the programming limit for RTS, where the task switching frequency is high. In parallel with the improvement of software scheduling algorithms, their implementation in hardware has been proposed and validated to relieve the processor of scheduling overhead and reduce RTOS-specific overhead.

摘要

实时系统(RTS)的基本要求之一是需要保证关键任务的实时确定性。任务执行速率、操作系统(OS)开销以及任务上下文切换时间只是可能在采用软调度器的RTS中导致抖动和错过期限的几个参数。只要周期性偏差和最坏情况响应时间的累积值小于该应用所需的响应时间,易受抖动影响的控制系统就可用于硬实时系统的控制。本文介绍了基于不同指令集架构(ISA)、定制中央处理器(CPU)数据通路、专用硬件线程上下文和硬件实时操作系统(RTOS)实现的现场可编程门阵列(FPGA)软核处理器集成。基于现有工作问题,一个可能对RTS性能产生负面影响的参数是操作系统带来的额外成本。调度和线程上下文切换操作会显著降低RTS的编程极限,其中任务切换频率很高。在改进软件调度算法的同时,已提出并验证了其在硬件中的实现,以减轻处理器的调度开销并减少特定于RTOS的开销。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/9ed0/10280498/47ccd7e8d362/peerj-cs-09-1300-g011.jpg
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https://cdn.ncbi.nlm.nih.gov/pmc/blobs/9ed0/10280498/cacca24033d0/peerj-cs-09-1300-g008.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/9ed0/10280498/e26b877ef900/peerj-cs-09-1300-g009.jpg
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Today's computing challenges: opportunities for computer hardware design.
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