Faculty of Electronics, Telecommunications and Information Technology, "Gheorghe Asachi" Technical University of Iasi, 700506 Iasi, Romania.
Technical Sciences Academy of Romania-ASTR, 030167 Bucharest, Romania.
Sensors (Basel). 2023 Jul 7;23(13):6220. doi: 10.3390/s23136220.
In this paper, we present two systolic array algorithms for efficient Very-Large-Scale Integration (VLSI) implementations of the 1-D Modified Discrete Sine Transform (MDST) using the systolic array architectural paradigm. The new algorithms decompose the computation of the MDST into modular and regular computational structures called pseudo-circular correlation and pseudo-cycle convolution. The two computational structures for pseudo-circular correlation and pseudo-cycle convolution both have the same form. This feature can be exploited to significantly reduce the hardware complexity since the two computational structures can be computed on the same linear systolic array. Moreover, the second algorithm can be used to further reduce the hardware complexity by replacing the general multipliers from the first one with multipliers with a constant that have a significantly reduced complexity. The resulting VLSI architectures have all the advantages of a cycle convolution and circular correlation based systolic implementations, such as high-speed using concurrency, an efficient use of the VLSI technology due to its local and regular interconnection topology, and low I/O cost. Moreover, in both architectures, a cost-effective application of an obfuscation technique can be achieved with low overheads.
在本文中，我们提出了两种用于高效超大规模集成电路（VLSI）实现的脉动阵列算法，使用脉动阵列架构范例来实现一维修正离散正弦变换（MDST）。新算法将 MDST 的计算分解为称为伪循环相关和伪循环卷积的模块化和规则计算结构。这两个用于伪循环相关和伪循环卷积的计算结构具有相同的形式。这个特性可以被利用来显著降低硬件复杂度，因为这两个计算结构可以在同一个线性脉动阵列上进行计算。此外，第二个算法可以通过用具有大大降低复杂度的常数的乘法器替换第一个算法中的通用乘法器来进一步降低硬件复杂度。所得的 VLSI 架构具有基于循环卷积和循环相关的脉动实现的所有优点，例如使用并发性实现高速、由于其局部和规则的互连拓扑而高效利用 VLSI 技术，以及低 I/O 成本。此外，在这两个架构中，都可以以较低的开销实现具有成本效益的混淆技术的应用。
