Oh Sungjin, Song Hyunsoo, Slager Nathan, Ruiz Jose Roberto Lopez, Park Sung-Yun, Yoon Euisik
IEEE Trans Biomed Circuits Syst. 2023 Aug;17(4):741-753. doi: 10.1109/TBCAS.2023.3298662. Epub 2023 Oct 6.
We report a power-efficient analog front-end integrated circuit (IC) for multi-channel, dual-band subcortical recordings. In order to achieve high-resolution multi-channel recordings with low power consumption, we implemented an incremental ΔΣ ADC (IADC) with a dynamic zoom-and-track scheme. This scheme continuously tracks local field potential (LFP) and adaptively adjusts the input dynamic range (DR) into a zoomed sub-LFP range to resolve tiny action potentials. Thanks to the reduced DR, the oversampling rate of the IADC can be reduced by 64.3% compared to the conventional approach, leading to significant power reduction. In addition, dual-band recording can be easily attained because the scheme continuously tracks LFPs without additional on-chip hardware. A prototype four-channel front-end IC has been fabricated in 180 nm standard CMOS processes. The IADC achieved 11.3-bit ENOB at 6.8 μW, resulting in the best Walden and SNDR FoMs, 107.9 fJ/c-s and 162.1 dB, respectively, among two different comparison groups: the IADCs reported up to date in the state-of-the-art neural recording front-ends; and the recent brain recording ADCs using similar zooming or tracking techniques to this work. The intrinsic dual-band recording feature reduces the post-processing FPGA resources for subcortical signal band separation by >45.8%. The front-end IC with the zoom-and-track IADC showed an NEF of 5.9 with input-referred noise of 8.2 μV, sufficient for subcortical recording. The performance of the whole front-end IC was successfully validated through in vivo animal experiments.
我们报告了一种用于多通道、双波段皮层下记录的低功耗模拟前端集成电路(IC)。为了在低功耗下实现高分辨率多通道记录,我们采用了一种具有动态缩放跟踪方案的增量ΔΣ模数转换器(IADC)。该方案持续跟踪局部场电位(LFP),并将输入动态范围(DR)自适应调整到缩放后的子LFP范围内,以解析微小的动作电位。由于动态范围减小,与传统方法相比,IADC的过采样率可降低64.3%,从而显著降低功耗。此外,由于该方案无需额外的片上硬件即可持续跟踪LFP,因此可以轻松实现双波段记录。一个四通道前端IC原型已采用180 nm标准CMOS工艺制造。该IADC在6.8 μW功耗下实现了11.3位有效噪声带宽(ENOB),在两个不同的比较组中分别获得了最佳的瓦尔登(Walden)和信噪失真比(SNDR)优值,分别为107.9 fJ/c-s和162.1 dB:一组是迄今为止在最先进的神经记录前端中报道的IADC;另一组是近期采用与本工作类似的缩放或跟踪技术的脑记录模数转换器。其固有的双波段记录功能使皮层下信号频段分离的后处理现场可编程门阵列(FPGA)资源减少了45.8%以上。具有缩放跟踪IADC的前端IC的噪声效率因子(NEF)为5.9,输入参考噪声为8.2 μV,足以用于皮层下记录。通过体内动物实验成功验证了整个前端IC的性能。