Sun Ying, Guo Zhichuan
National Network New Media Engineering Research Center, Institute of Acoustics, Chinese Academy of Sciences, No. 21, North Fourth Ring Road, Haidian District, Beijing 100190, China.
School of Electronic, Electrical and Communication Engineering, University of Chinese Academy of Sciences, No. 19(A), Yuquan Road, Shijingshan District, Beijing 100049, China.
Micromachines (Basel). 2023 Aug 5;14(8):1560. doi: 10.3390/mi14081560.
To meet the evolving demands of programmable networks and address the limitations of traditional fixed-type protocol parsers, we propose a dynamic and configurable low-latency parser implemented on an FPGA. The architecture consists of three protocol analysis modules and a TCAM-SRAM. Latency is reduced by optimizing the state machine and parallel extraction matching. At the same time, we introduce the chain mapping idea and container concept to formulate the matching and extraction rules of table entries and enhance the extensibility of the parser. Furthermore, our system supports dynamic configuration through SDN control, allowing flexible adaptation to diverse scenarios. Our design has been verified and simulated with a cocotb-based framework. The resulting architecture is implemented on Xilinx Ultrascale+ FPGAs and supports a throughput of more than 80 Gbps, with a maximum latency of only 36 nanoseconds for L4 protocol parsing.
为了满足可编程网络不断发展的需求并解决传统固定类型协议解析器的局限性，我们提出了一种在FPGA上实现的动态可配置低延迟解析器。该架构由三个协议分析模块和一个TCAM-SRAM组成。通过优化状态机和并行提取匹配来降低延迟。同时，我们引入链映射思想和容器概念来制定表项的匹配和提取规则，并增强解析器的可扩展性。此外，我们的系统支持通过SDN控制进行动态配置，从而能够灵活适应各种场景。我们的设计已通过基于cocotb的框架进行了验证和模拟。最终架构在赛灵思Ultrascale+ FPGA上实现，支持超过80 Gbps的吞吐量，对于L4协议解析，最大延迟仅为36纳秒。
