Song Xiaoyong, Lu Rui, Guo Zhichuan
National Network New Media Engineering Research Center, Institute of Acoustics, Chinese Academy of Sciences, No. 21, North Fourth Ring Road, Haidian District, Beijing 100190, China.
School of Electronic, Electrical and Communication Engineering, University of Chinese Academy of Sciences, No. 19(A), Yuquan Road, Shijingshan District, Beijing 100049, China.
Micromachines (Basel). 2024 Mar 27;15(4):449. doi: 10.3390/mi15040449.
As the key module of programmable switches or the SmartNIC card, the packet processing pipeline undertakes the task of packet forwarding and processing. However, the current pipeline for the FPGA-based SmartNIC is inflexible, and the related reconfigurable commercial device designs are closed-source. To solve this problem, this paper proposes a high-performance reconfigurable pipeline design, which has fully reconfigurable match-action units, supporting various network functions by its flexible reconfiguration. The fields of the match key and the size of the match table can be reconfigured without recompiling the HDL code or modifying the hardware. The processing rules and action instructions for the pipeline can be dynamically installed by the configuration module at runtime. We implement our design on the Xilinx Alveo U200 board with a Virtex UltraScale+ XCU200-2FSGD2104E FPGA and show that the designed pipeline supports fast reconfiguration to implement new network functions and that the throughput of the designed pipeline reaches 100 Gbps with low latency.
作为可编程交换机或智能网卡的关键模块，分组处理流水线承担着分组转发和处理的任务。然而，当前基于FPGA的智能网卡流水线缺乏灵活性，且相关的可重构商业设备设计是闭源的。为了解决这一问题，本文提出了一种高性能可重构流水线设计，它具有完全可重构的匹配动作单元，通过灵活的重构支持各种网络功能。匹配关键字段和匹配表大小可以在不重新编译HDL代码或修改硬件的情况下进行重构。流水线的处理规则和动作指令可以由配置模块在运行时动态安装。我们在采用Virtex UltraScale+ XCU200-2FSGD2104E FPGA的赛灵思Alveo U200板上实现了我们的设计，并表明所设计的流水线支持快速重构以实现新的网络功能，且所设计流水线的吞吐量达到100 Gbps且延迟较低。
