Balasubramanian Padmanabhan, Liu Weichen
School of Computer Science and Engineering, Nanyang Technological University, Singapore, Singapore.
PLoS One. 2023 Oct 5;18(10):e0289569. doi: 10.1371/journal.pone.0289569. eCollection 2023.
Addition is a fundamental computer arithmetic operation that is widely performed in microprocessors, digital signal processors, and application-specific processors. The design of a high-speed and energy-efficient adder is thus useful and important for practical applications. In this context, this paper presents the designs of novel asynchronous carry look-ahead adders (CLAs) viz. a standard CLA (SCLA) and a block CLA (BCLA). The proposed CLAs are monotonic, dual-rail encoded, and are realized according to return-to-zero handshake (RZH) and return-to-one handshake (ROH) protocols using a 28-nm CMOS process technology. The proposed BCLA has a slight edge over the proposed SCLA, and the proposed BCLA reports the following optimizations in design metrics such as cycle time (delay), area, and power compared to a recently presented state-of-the-art asynchronous CLA for a 32-bit addition: (i) 32.6% reduction in cycle time, 29% reduction in area, 4.3% reduction in power, and 35.5% reduction in energy for RZH, and (ii) 31.4% reduction in cycle time, 28.9% reduction in area, 4.4% reduction in power, and 34.4% reduction in energy for ROH. Also, the proposed BCLA reports reductions in cycle time and power/energy compared to many other asynchronous adders.
加法是一种基本的计算机算术运算，在微处理器、数字信号处理器和专用处理器中广泛执行。因此，设计高速且节能的加法器对于实际应用而言既有用又重要。在此背景下，本文介绍了新型异步先行进位加法器（CLA）的设计，即标准CLA（SCLA）和块CLA（BCLA）。所提出的CLA是单调的、双轨编码的，并使用28纳米CMOS工艺技术根据归零握手（RZH）和回一握手（ROH）协议实现。所提出的BCLA比所提出的SCLA略有优势，并且与最近提出的用于32位加法的最先进异步CLA相比，所提出的BCLA在诸如周期时间（延迟）、面积和功耗等设计指标上实现了以下优化：（i）对于RZH，周期时间减少32.6%，面积减少29%，功耗减少4.3%，能量减少35.5%；（ii）对于ROH，周期时间减少31.4%，面积减少28.9%，功耗减少4.4%，能量减少34.4%。此外，与许多其他异步加法器相比，所提出的BCLA在周期时间以及功耗/能量方面也有所减少。
