School of Computer Science and Engineering, Nanyang Technological University, Singapore.
Department of Industrial Engineering, Technical University of Sofia, Sofia, Bulgaria.
PLoS One. 2020 Feb 3;15(2):e0228343. doi: 10.1371/journal.pone.0228343. eCollection 2020.
Multiplication is a widely used arithmetic operation that is frequently encountered in micro-processing and digital signal processing. Multiplication is implemented using a multiplier, and recently, QDI asynchronous array multipliers were presented in the literature utilizing delay-insensitive double-rail data encoding and four-phase return-to-zero (RTZ) handshaking and four-phase return-to-one (RTO) handshaking. In this context, this article makes two contributions: (i) the design of a new asynchronous partial product generator, and (ii) the design of a new asynchronous half adder. We analyze the usefulness of the proposed partial product generator and the proposed half adder to efficiently realize QDI array multipliers. When the new partial product generator and half adder are used along with our indicating full adder, significant reductions are achieved in the design metrics compared to the optimum QDI array multiplier reported in the literature. The cycle time is reduced by 17%, the area is reduced by 16.1%, the power is reduced by 15.3%, and the product of power and cycle time is reduced by 29.6% with respect to RTZ handshaking. On the other hand, the cycle time is reduced by 13%, the area is reduced by 16.1%, the power is reduced by 15.2%, and the product of power and cycle time is reduced by 26.1% with respect to RTO handshaking. Further, the RTO handshaking is found to be preferable to RTZ handshaking to achieve slightly improved optimizations in the design metrics. The QDI array multipliers were realized using a 32/28nm complementary metal oxide semiconductor (CMOS) process technology.
乘法是一种广泛使用的算术运算，在微处理和数字信号处理中经常遇到。乘法是通过乘法器来实现的，最近，文献中提出了 QDI 异步阵列乘法器，它利用了延迟不敏感的双轨数据编码和四相归零（RTZ）握手以及四相返回一（RTO）握手。在这种情况下，本文做出了两个贡献：（i）设计了一种新的异步部分积生成器，（ii）设计了一种新的异步半加器。我们分析了所提出的部分积生成器和所提出的半加器在有效地实现 QDI 阵列乘法器方面的有用性。当使用新的部分积生成器和半加器以及我们的指示全加器时，与文献中报告的最佳 QDI 阵列乘法器相比，设计指标有了显著的降低。与 RTZ 握手相比，时钟周期减少了 17%，面积减少了 16.1%，功率减少了 15.3%，功率和时钟周期的乘积减少了 29.6%。另一方面，与 RTO 握手相比，时钟周期减少了 13%，面积减少了 16.1%，功率减少了 15.2%，功率和时钟周期的乘积减少了 26.1%。此外，发现 RTO 握手比 RTZ 握手更有利于实现设计指标的略微改进。使用 32/28nm 互补金属氧化物半导体（CMOS）工艺技术实现了 QDI 阵列乘法器。
