Xu Yixin, Zhao Zijian, Xiao Yi, Yu Tongguang, Mulaosmanovic Halid, Kleimaier Dominik, Duenkel Stefan, Beyer Sven, Gong Xiao, Joshi Rajiv, Hu Xiaobo, Wen Shixian, Rios Amanda Sofie, Lekkala Kiran, Itti Laurent, Homan Eric, George Sumitha, Narayanan Vijaykrishnan, Ni Kai
Pennsylvania State University, State College, PA 16802, USA.
University of Notre Dame, Notre Dame, IN 46556, USA.
Sci Adv. 2024 Jan 19;10(3):eadk1525. doi: 10.1126/sciadv.adk1525. Epub 2024 Jan 17.
Field programmable gate array (FPGA) is widely used in the acceleration of deep learning applications because of its reconfigurability, flexibility, and fast time-to-market. However, conventional FPGA suffers from the trade-off between chip area and reconfiguration latency, making efficient FPGA accelerations that require switching between multiple configurations still elusive. Here, we propose a ferroelectric field-effect transistor (FeFET)-based context-switching FPGA supporting dynamic reconfiguration to break this trade-off, enabling loading of arbitrary configuration without interrupting the active configuration execution. Leveraging the intrinsic structure and nonvolatility of FeFETs, compact FPGA primitives are proposed and experimentally verified. The evaluation results show our design shows a 63.0%/74.7% reduction in a look-up table (LUT)/connection block (CB) area and 82.7%/53.6% reduction in CB/switch box power consumption with a minimal penalty in the critical path delay (9.6%). Besides, our design yields significant time savings by 78.7 and 20.3% on average for context-switching and dynamic reconfiguration applications, respectively.
现场可编程门阵列（FPGA）因其可重构性、灵活性和快速上市时间而被广泛应用于深度学习应用的加速。然而，传统FPGA在芯片面积和重新配置延迟之间存在权衡，使得需要在多种配置之间切换的高效FPGA加速仍然难以实现。在此，我们提出一种基于铁电场效应晶体管（FeFET）的上下文切换FPGA，支持动态重新配置以打破这种权衡，能够在不中断当前活动配置执行的情况下加载任意配置。利用FeFET的固有结构和非易失性，我们提出了紧凑的FPGA原语并进行了实验验证。评估结果表明，我们的设计在查找表（LUT）/连接块（CB）面积上减少了63.0%/74.7%，在CB/开关盒功耗上减少了82.7%/53.6%，而关键路径延迟的增加最小（9.6%）。此外，我们的设计在上下文切换和动态重新配置应用中平均分别节省了78.7%和20.3%的时间。
