Department of Electronics and Communications Engineering, Gokaraju Rangaraju Institute of Engineering and Technology, Hyderabad, 500090, India.
Department of Electrical, Electronics and Communication Engineering, GITAM University, Visakhaptnam, Andhra Pradesh, 530045, India.
F1000Res. 2023 Sep 21;12:1182. doi: 10.12688/f1000research.126067.1. eCollection 2023.
This paper presents an efficient two-dimensional (2-D) finite impulse response (FIR) filter using block processing for two different symmetries. Architectures for a general filter (without symmetry) and two symmetrical filters (diagonal and quadrantal symmetry) are implemented. The proposed architectures need fewer multipliers because of the symmetry of the filter coefficients. A distributed arithmetic (DA)- based multiplication method is used in the proposed architecture. A dual-port memory-based lookup table (DP-MLUT) is used in the multiplication instead of lookup-table (LUT) to reduce the area and power of the FIR filter. The filter's throughput is increased by using block processing. Memory reuse and memory sharing methods are introduced, which reduces the need for many registers and hence the circuit complexity. The architectures are written in Verilog Hardware Description Language and synthesized using Genus Synthesis tool-19.1 in 45nm technology with a generic library of Cadence vendor constraints. The synthesis tool generates the area, delay, and power reports. Power consumption of architectures is calculated with an image size of 64 X 64 and at 20 MHz frequency. Compared to existing architectures, the synthesis results show improvements in power, area, area delay product (ADP), and power delay product (PDP). The proposed MLUT-based 2-D block Quadrantal Symmetry Filter (QSF) for length 8 with block size 4 consumes 58.94% less power, occupies 59.5% less area, 48.44% less ADP and 47.78% less PDP compared to best existing methods. A novel DA-based 2-D block FIR filter architecture with various symmetries is realized. Symmetry is incorporated into the filter coefficients to minimize the number of multipliers. The LUT size is optimized by odd multiples or even multiples storage techniques. Also, the overall area of the architecture is decreased by DP-LUT-based multipliers. The proposed filter architecture is area-power-efficient. It is best suited for applications that have fixed coefficients.
本文提出了一种使用块处理的高效二维（2-D）有限脉冲响应（FIR）滤波器，适用于两种不同的对称性。实现了一般滤波器（无对称性）和两种对称滤波器（对角对称性和象限对称性）的架构。由于滤波器系数的对称性，所提出的架构需要更少的乘法器。在提出的架构中使用基于分布式算术（DA）的乘法方法。在乘法中使用基于双端口存储器的查找表（DP-MLUT）代替查找表（LUT），以减小 FIR 滤波器的面积和功耗。通过使用块处理提高滤波器的吞吐量。引入了存储器重用和存储器共享方法，减少了对许多寄存器的需求，从而降低了电路的复杂性。架构采用 Verilog 硬件描述语言编写，并使用 Genus Synthesis 工具-19.1 在 45nm 技术下使用 Cadence 供应商约束的通用库进行综合。综合工具生成面积、延迟和功耗报告。架构的功耗是根据 64 X 64 的图像大小和 20 MHz 的频率计算的。与现有架构相比，综合结果在功率、面积、面积延迟乘积（ADP）和功率延迟乘积（PDP）方面都有所提高。与现有最佳方法相比，所提出的基于 MLUT 的 2-D 块象限对称滤波器（QSF）的长度为 8，块大小为 4，可节省 58.94%的功率，占用 59.5%的面积减少 48.44%的 ADP 和 47.78%的 PDP。实现了具有各种对称性的新型基于 DA 的 2-D 块 FIR 滤波器架构。将对称性纳入滤波器系数中，以最小化乘法器的数量。通过奇数倍或偶数倍存储技术优化 LUT 大小。此外，基于 DP-LUT 的乘法器减小了架构的整体面积。所提出的滤波器架构在面积和功耗方面具有效率。它最适合具有固定系数的应用。
