Ijaz Qaiser, Kidane Hiliwi Leake, Bourennane El-Bay, Ochoa-Ruiz Gilberto
ImViA Laboratory, University of Burgundy, 21000 Dijon, France.
Department of Computer Systems Engineering, Islamia University of Bahawalpur, Bahawalpur 63100, Pakistan.
Micromachines (Basel). 2023 Oct 7;14(10):1913. doi: 10.3390/mi14101913.
The paper proposes two architectures for a dynamically scalable network-on-chip (NoC) for dynamically reconfigurable intellectual properties (IPs) to save power. The first architecture is a run-time scalable column-based NoC, where the columns of the NoC are scaled up and down at run-time depending on the demands to connect reconfigurable IPs. The second architecture is an extension of the first, where both the rows and columns of the NoC are dynamically scaled up and down on demand. A robust control manager is developed to control the IP and sub-NoC reconfigurations by optimizing the reconfiguration costs. The proposed architectures have been implemented and tested in actual prototypes on a Virtex 6 FPGA mounted on the ML605 board. The results show that dynamically scalable architectures are capable of significant power reduction as compared to traditional static architectures for the same size of the NoC. It is anticipated that the scalable NoC can be very useful for sharing the FPGA resources among IPs at runtime.
本文提出了两种用于动态可重配置知识产权（IP）的动态可扩展片上网络（NoC）架构，以节省功耗。第一种架构是基于列的运行时可扩展NoC，其中NoC的列根据连接可重配置IP的需求在运行时进行扩展和收缩。第二种架构是第一种架构的扩展，其中NoC的行和列都可根据需求动态地进行扩展和收缩。开发了一个健壮的控制管理器，通过优化重配置成本来控制IP和子NoC的重配置。所提出的架构已在安装在ML605板上的Virtex 6 FPGA的实际原型中实现并进行了测试。结果表明，与相同规模的传统静态架构相比，动态可扩展架构能够显著降低功耗。预计可扩展NoC在运行时可用于在IP之间共享FPGA资源，非常有用。
