Noh Tae Hyeon, Chen Simin, Kim Hyo-Bae, Jin Taewon, Park Seoung Min, An Seong Ui, Sun Xinkai, Kim Jaekyun, Han Jae-Hoon, Ahn Ji-Hoon, Ahn Dae-Hwan, Kim Younghyun
Department of Photonics and Nanoelectronics, BK21 FOUR ERICA-ACE Center, Hanyang University, Ansan 15588, Republic of Korea.
Department of Materials Science and Chemical Engineering, Hanyang University, Ansan, Republic of Korea.
Nanoscale. 2024 Sep 12;16(35):16467-16476. doi: 10.1039/d4nr02393e.
Conventional DRAM, consisting of one transistor and one capacitor (1T1C), requires periodic data refresh processes due to its limited retention time and data-destructive read operation. Here, we propose and demonstrate a novel 3D-DRAM memory scheme available with a single transistor and a single ferroelectric field-effect transistor (FeFET) DRAM (2T0C-FeDRAM), which offers extended retention time and non-destructive read operation. This architecture uses a back-end-of-line (BEOL)-compatible amorphous oxide semiconductor (AOS) that is suitable for increasing DRAM cell density. Notably, the device structures of a double gate a-ITZO/a-IGZO FeFET, used for data storage and reading, are engineered to achieve an enlarged memory window (MW) of 1.5 V and a prolonged retention time of 10 s. This is accomplished by a double gate and an a-ITZO/a-IGZO heterostructure channel to enable efficient polarization control in hafnium-zirconium oxide (HZO) layers. We present successful program/erase operations of the double gate a-ITZO/a-IGZO FeFET through incremental step pulse programming (ISPP), demonstrating multi-level states with remarkable retention characteristics. Most importantly, we perform 2T0C-FeDRAM operations by electrically connecting the double gate a-ITZO/a-IGZO FeFET and the a-ITZO FET. Leveraging the impressive performance of the double gate a-ITZO/a-IGZO FeFET technology, we have effectively showcased an exceptionally record-long retention time exceeding 2000 s and 4-bit multi-level states, positioning it as a robust contender among emerging memory solutions in the era of artificial intelligence.
传统动态随机存取存储器（DRAM）由一个晶体管和一个电容器（1T1C）组成，由于其有限的保持时间和数据破坏性读取操作，需要定期进行数据刷新过程。在此，我们提出并演示了一种新颖的3D-DRAM存储方案，该方案采用单个晶体管和单个铁电场效应晶体管（FeFET）DRAM（2T0C-FeDRAM），具有延长的保持时间和非破坏性读取操作。这种架构使用与后端制程（BEOL）兼容的非晶氧化物半导体（AOS），适合于提高DRAM单元密度。值得注意的是，用于数据存储和读取的双栅a-ITZO/a-IGZO FeFET的器件结构经过设计，可实现1.5 V的扩大存储窗口（MW）和10 s的延长保持时间。这是通过双栅和a-ITZO/a-IGZO异质结构沟道实现的，以便在铪锆氧化物（HZO）层中实现有效的极化控制。我们通过增量阶梯脉冲编程（ISPP）展示了双栅a-ITZO/a-IGZO FeFET的成功编程/擦除操作，证明了具有显著保持特性的多电平状态。最重要的是，我们通过将双栅a-ITZO/a-IGZO FeFET与a-ITZO FET电连接来执行2T0C-FeDRAM操作。利用双栅a-ITZO/a-IGZO FeFET技术令人印象深刻的性能，我们有效地展示了超过2000 s的超长保持时间记录以及4位多电平状态，使其成为人工智能时代新兴存储解决方案中的有力竞争者。
