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一种基于随机热力学的逻辑门能量与信息分析方法。

An energy and information analysis method of logic gates based on stochastic thermodynamics.

作者信息

Ge Xiaohu, Ruan Muyao, Peng Xiaoxuan, Xiao Yong, Yang Yang

机构信息

School of Electronic Information and Communications, Huazhong University of Science and Technology, Wuhan 430074, Hubei, China.

International Joint Research Center of Green Communications and Networking, Huazhong University of Science and Technology, Wuhan 430074, Hubei, China.

出版信息

PNAS Nexus. 2024 Aug 26;3(9):pgae365. doi: 10.1093/pnasnexus/pgae365. eCollection 2024 Sep.

DOI:10.1093/pnasnexus/pgae365
PMID:39295948
原文链接:https://pmc.ncbi.nlm.nih.gov/articles/PMC11410042/
Abstract

To reduce the energy consumption of logic gates in digital circuits, the size of transistors approaches the mesoscopic scale, e.g. sub-7 nanometers. However, existing energy consumption analysis methods exhibit various deviation for logic gates when the nonequilibrium information processing of mesoscopic scale transistors with ultra-low voltages is analyzed. Based on the stochastic thermodynamics theory, an information energy ratio method is proposed for the energy consumption estimation of XOR gates composed of mesoscopic scale transistors. The proposed method provides a new insight to quantify the transformation between the information capacity and energy consumption for XOR gates and extending to other logic gates. Utilizing the proposed analysis method, the supply voltage of the parity check circuit can be optimized by numerical simulations without expensive and complex practical measurements. The information energy ratio is the first analytical method to quantify the energy and information transformation of logic gates at the mesoscopic scale.

摘要

为降低数字电路中逻辑门的能耗,晶体管尺寸已接近介观尺度,例如小于7纳米。然而,在分析具有超低电压的介观尺度晶体管的非平衡信息处理时,现有的能耗分析方法对逻辑门存在各种偏差。基于随机热力学理论,提出了一种信息能量比方法,用于估算由介观尺度晶体管组成的异或门的能耗。该方法为量化异或门的信息容量与能耗之间的转换提供了新的视角,并可推广到其他逻辑门。利用所提出的分析方法,无需进行昂贵且复杂的实际测量,通过数值模拟即可优化奇偶校验电路的电源电压。信息能量比是第一种用于量化介观尺度逻辑门的能量与信息转换的分析方法。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/de46/11410042/163dff509d49/pgae365f4.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/de46/11410042/52eb958c43ef/pgae365f1.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/de46/11410042/abbbfc178dca/pgae365f2.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/de46/11410042/177ba60f4c8b/pgae365f3.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/de46/11410042/163dff509d49/pgae365f4.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/de46/11410042/52eb958c43ef/pgae365f1.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/de46/11410042/abbbfc178dca/pgae365f2.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/de46/11410042/177ba60f4c8b/pgae365f3.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/de46/11410042/163dff509d49/pgae365f4.jpg

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本文引用的文献

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Vertical MoS transistors with sub-1-nm gate lengths.具有亚 1 纳米栅长的垂直 MoS 晶体管。
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Energy Efficiency Challenges of 5G Small Cell Networks.5G小蜂窝网络的能源效率挑战
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