School of Integrated Circuits, Tsinghua University, Beijing, China.
The Beijing National Research Center for Information Science and Technology (BNRist), Tsinghua University, Beijing, China.
Nature. 2022 Mar;603(7900):259-264. doi: 10.1038/s41586-021-04323-3. Epub 2022 Mar 9.
Ultra-scaled transistors are of interest in the development of next-generation electronic devices. Although atomically thin molybdenum disulfide (MoS) transistors have been reported, the fabrication of devices with gate lengths below 1 nm has been challenging. Here we demonstrate side-wall MoS transistors with an atomically thin channel and a physical gate length of sub-1 nm using the edge of a graphene layer as the gate electrode. The approach uses large-area graphene and MoS films grown by chemical vapour deposition for the fabrication of side-wall transistors on a 2-inch wafer. These devices have On/Off ratios up to 1.02 × 10 and subthreshold swing values down to 117 mV dec. Simulation results indicate that the MoS side-wall effective channel length approaches 0.34 nm in the On state and 4.54 nm in the Off state. This work can promote Moore's law of the scaling down of transistors for next-generation electronics.
超大规模晶体管是下一代电子设备发展的关注点。尽管已经报道了原子级薄的二硫化钼 (MoS) 晶体管，但制造栅长低于 1nm 的器件一直具有挑战性。在这里，我们展示了使用石墨烯层的边缘作为栅电极的具有原子级薄沟道和小于 1nm 的物理栅长的侧墙 MoS 晶体管。该方法使用大面积石墨烯和化学气相沉积生长的 MoS 薄膜，在 2 英寸晶圆上制造侧墙晶体管。这些器件的 On/Off 比高达 1.02×10，亚阈值摆幅低至 117mV·dec。模拟结果表明，MoS 侧墙有效沟道长度在 On 状态下接近 0.34nm，在 Off 状态下接近 4.54nm。这项工作可以推动晶体管向更小尺寸迈进，以实现下一代电子产品的摩尔定律。
