Zheng Xuesong, Wu Yifan, Dong Haitao, Liu Yizhi, Sang Pengpeng, Xiao Liyi, Zhan Xuepeng
School of Astronautics, Harbin Institute of Technology, Harbin 150001, China.
China Aerospace Components Engineering Center, Beijing 100094, China.
Micromachines (Basel). 2024 Aug 23;15(9):1060. doi: 10.3390/mi15091060.
Three-dimensional charge-trapping (CT) NAND flash memory has attracted extensive attention owing to its unique merits, including huge storage capacities, large memory densities, and low bit cost. The reliability property is becoming an important factor for NAND flash memory with multi-level-cell (MLC) modes like triple-level-cell (TLC) or quad-level-cell (QLC), which is seriously affected by the intervals between program (P) and erase (E) operations during P/E cycles. In this work, the impacts of the intervals between P&E cycling under different temperatures and P/E cycles were systematically characterized. The results are further analyzed in terms of program disturb (PD), read disturb (RD), and data retention (DR). It was found that fail bit counts (FBCs) during the high temperature (HT) PD process are much smaller than those of the room temperature (RT) PD process. Moreover, upshift error and downshift error dominate the HT PD and RT PD processes, respectively. To improve the memory reliability of 3D CT TLC NAND, different intervals between P&E operations should be adopted considering the operating temperatures. These results could provide potential insights to optimize the lifetime of NAND flash-based memory systems.
三维电荷俘获（CT）NAND闪存因其独特的优点，包括巨大的存储容量、高存储密度和低位成本，而备受关注。对于具有诸如三层单元（TLC）或四层单元（QLC）等多级单元（MLC）模式的NAND闪存，可靠性正成为一个重要因素，这在P/E循环期间受到编程（P）和擦除（E）操作之间的间隔的严重影响。在这项工作中，系统地表征了在不同温度下P&E循环之间的间隔以及P/E循环的影响。根据编程干扰（PD）、读取干扰（RD）和数据保留（DR）对结果进行了进一步分析。结果发现，高温（HT）PD过程中的失效位计数（FBC）远小于室温（RT）PD过程中的失效位计数。此外，上移误差和下移误差分别主导着HT PD和RT PD过程。为了提高3D CT TLC NAND的存储可靠性，应根据工作温度采用不同的P&E操作间隔。这些结果可为优化基于NAND闪存的存储系统的寿命提供潜在的见解。
