Hu Jianing, Wan Jialong, Shen Yi, Zhao Wei, Luo Jiang
School of Electronics and Information, Hangzhou Dianzi University, Hangzhou 310018, China.
School of Microelectronics, South China University of Technology, Guangzhou 511442, China.
Micromachines (Basel). 2024 Aug 26;15(9):1077. doi: 10.3390/mi15091077.
This paper introduces a high-gain wideband power amplifier (PA) designed for V-band applications, operating across 52 to 65 GHz. The proposed PA design employs a combination of techniques, including pole-gain distribution, base-capacitive peaking, and the parallel configuration of multiple small-sized transistors. These strategies enable significant bandwidth extension while maintaining high gain, substantial output power, and a compact footprint. A two-stage PA using the combination technique was developed and fabricated in a 130 nm SiGe BiCMOS process. The PA prototype achieved a peak gain of 27.3 dB at 64 GHz, with a 3 dB bandwidth exceeding 13 GHz and a fractional bandwidth greater than 22.2%. It delivered a maximum saturated output power of 19.7 dBm and an output 1 dB compression point of 18 dBm. Moreover, the PA chip occupied a total silicon area of 0.57 mm, including all testing pads with a compact core size of 0.198 mm.
本文介绍了一种专为V波段应用设计的高增益宽带功率放大器（PA），其工作频率范围为52至65GHz。所提出的PA设计采用了多种技术的组合，包括极点增益分布、基极电容峰值化以及多个小尺寸晶体管的并联配置。这些策略在保持高增益、高输出功率和紧凑尺寸的同时，实现了显著的带宽扩展。采用该组合技术的两级PA在130nm SiGe BiCMOS工艺中进行了开发和制造。该PA原型在64GHz时实现了27.3dB的峰值增益，3dB带宽超过13GHz，分数带宽大于22.2%。它提供了19.7dBm的最大饱和输出功率和18dBm的输出1dB压缩点。此外，PA芯片的总硅面积为0.57mm²，包括所有测试焊盘，紧凑的核心尺寸为0.198mm²。
