Kim Jong-Hyun, Kim Seung-Hwan, Yu Hyun-Yong
Department of Semiconductor Systems Engineering, Korea University, 145, Anam-ro, Seongbuk-gu, Seoul, 02841, South Korea.
Center for Spintronics, Korea Institute of Science and Technology (KIST), 5, Hwarang-ro 14-gil, Seongbuk-gu, Seoul, 02792, South Korea.
Small. 2024 Dec;20(50):e2405459. doi: 10.1002/smll.202405459. Epub 2024 Oct 2.
A van der Waals (vdW) α-InSe ferroelectric semiconductor channel-based field-effect transistor (FeS-FET) has emerged as a next-generation electronic device owing to its versatility in various fields, including neuromorphic computing, nonvolatile memory, and optoelectronics. However, screening charges cause by the imperfect surface morphology of vdW α-InSe inhibiting electrical polarization remain an unresolved issue. In this study, for the first time, a method is elucidated to recover the inherent electric polarization in both in- and out-of-plane directions of the α-InSe channel based on post-exfoliation annealing (PEA) and improve the electrical performance of vdW FeS-FETs. Following PEA, an ultra-thin InSeO layer formed on the top surface of the α-InSe channel is demonstrated to passivate surface defects and enhance the electrical performance of FeS-FETs. The on/off current ratio of the α-InSe FeS-FET has increased from 5.99 to 1.84 × 10, and the magnitude of ferroelectric resistance switching has increased from 1.20 to 26.01. Moreover, the gate-modulated artificial synaptic operation of the α-InSe FeS-FET is demonstrated and illustrate the significance of the engineered interface in the vdW FeS-FET for its application to multifunctional devices. The proposed α-InSe FeS-FET is expected to provide a significant breakthrough for advanced memory devices and neuromorphic computing.
基于范德华(vdW)α-InSe铁电半导体沟道的场效应晶体管(FeS-FET),因其在神经形态计算、非易失性存储器和光电子学等各个领域的多功能性,已成为一种下一代电子器件。然而,由vdW α-InSe不完美的表面形态导致的屏蔽电荷抑制电极化,仍然是一个未解决的问题。在本研究中,首次阐明了一种基于剥离后退火(PEA)的方法,以恢复α-InSe沟道面内和面外方向的固有电极化,并改善vdW FeS-FET的电学性能。经过PEA后,在α-InSe沟道顶表面形成的超薄InSeO层被证明可以钝化表面缺陷并提高FeS-FET的电学性能。α-InSe FeS-FET的开/关电流比从5.99提高到1.84×10,铁电电阻切换幅度从1.20提高到26.01。此外,还展示了α-InSe FeS-FET的栅极调制人工突触操作,并说明了vdW FeS-FET中工程界面对于其在多功能器件中的应用的重要性。所提出的α-InSe FeS-FET有望为先进存储器件和神经形态计算提供重大突破。