Suppr超能文献

使用顺序等离子体原子层沉积提高氧化铪薄膜的电荷俘获性能。

Enhancing Charge Trapping Performance of Hafnia Thin Films Using Sequential Plasma Atomic Layer Deposition.

作者信息

Kim So-Won, Yoo Jae-Hoon, Park Won-Ji, Lee Chan-Hee, Lee Joung-Ho, Kim Jong-Hwan, Uhm Sae-Hoon, Lee Hee-Chul

机构信息

Department of Advanced Materials Engineering, Tech University of Korea, Siheung 15073, Republic of Korea.

Korea Evaluation Institute of Industrial Technology, Seoul 06152, Republic of Korea.

出版信息

Nanomaterials (Basel). 2024 Oct 21;14(20):1686. doi: 10.3390/nano14201686.

Abstract

We aimed to fabricate reliable memory devices using HfO, which is gaining attention as a charge-trapping layer material for next-generation NAND flash memory. To this end, a new atomic layer deposition process using sequential remote plasma (RP) and direct plasma (DP) was designed to create charge-trapping memory devices. Subsequently, the operational characteristics of the devices were analyzed based on the thickness ratio of thin films deposited using the sequential RP and DP processes. As the thickness of the initially RP-deposited thin film increased, the memory window and retention also increased, while the interface defect density and leakage current decreased. When the thickness of the RP-deposited thin film was 7 nm, a maximum memory window of 10.1 V was achieved at an operating voltage of ±10 V, and the interface trap density (D) reached a minimum value of 1.0 × 10 eVcm. Once the RP-deposited thin film reaches a certain thickness, the ion bombardment effect from DP on the substrate is expected to decrease, improving the Si/SiO/HfO interface and thereby enhancing device endurance and reliability. This study confirmed that the proposed sequential RP and DP deposition processes could resolve issues related to unstable interface layers, improve device performance, and enhance process throughput.

摘要

我们旨在使用HfO制造可靠的存储器件,HfO作为下一代NAND闪存的电荷俘获层材料正受到关注。为此,设计了一种使用顺序远程等离子体(RP)和直接等离子体(DP)的新原子层沉积工艺来制造电荷俘获存储器件。随后,基于使用顺序RP和DP工艺沉积的薄膜的厚度比分析了器件的工作特性。随着最初RP沉积薄膜厚度的增加,存储窗口和保持特性也增加,而界面缺陷密度和漏电流降低。当RP沉积薄膜的厚度为7 nm时,在±10 V的工作电压下实现了10.1 V的最大存储窗口,并且界面陷阱密度(D)达到了1.0×10 eVcm的最小值。一旦RP沉积薄膜达到一定厚度,预计DP对衬底的离子轰击效应会降低,从而改善Si/SiO/HfO界面,进而提高器件的耐久性和可靠性。本研究证实,所提出的顺序RP和DP沉积工艺可以解决与不稳定界面层相关的问题,提高器件性能,并提高工艺产量。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/7edd/11509989/27a8eef26b16/nanomaterials-14-01686-g001.jpg

文献AI研究员

20分钟写一篇综述,助力文献阅读效率提升50倍。

立即体验

用中文搜PubMed

大模型驱动的PubMed中文搜索引擎

马上搜索

文档翻译

学术文献翻译模型,支持多种主流文档格式。

立即体验