Gholami Mohammad, Movahedi Maryam, Amirzadeh Zaman
Department of Electrical Engineering, Faculty of Engineering and Technology, University of Mazandaran, Babolsar, Iran.
Department of Electrical Engineering, Aryan Institute of Science and Technology, Babol, Iran.
Heliyon. 2024 Nov 19;10(23):e40486. doi: 10.1016/j.heliyon.2024.e40486. eCollection 2024 Dec 15.
This paper was focused on logic gates, D-latch, parallel-parallel shift-registers, and parallel-series shift registers, which are used as basic circuits in numerous circuits as well as computational and comparative units. To design proposed shift registers, D-latch which is the vital gate, is designed carefully for minimum size, decreasing number of cells and good performance for delay. The proposed level-sensitive parallel-in parallel-out () shift registers with reset terminal and with both set and reset terminals (single-layer and multi-layer), edge-sensitive shift registers with reset and set/reset abilities (single-layer and multi-layer), and the parallel-in serial-out () shift registers were designed using the proposed D-latches. Simulations show that the proposed level-sensitive shift-register set and reset terminals has cells, 13 μm occupied area, and delay of about cycles of QCA clock. In addition, the proposed edge-sensitive shift-register circuit with set-and-reset pins has cells, .17 μm occupied area, and delay of about cycles of QCA clocks. All designs and simulation results were made in the QCADesigner software.
本文聚焦于逻辑门、D锁存器、并行-并行移位寄存器和并行-串行移位寄存器，这些被用作众多电路以及计算和比较单元中的基本电路。为了设计所提出的移位寄存器，作为关键门的D锁存器经过精心设计，以实现最小尺寸、减少单元数量并具备良好的延迟性能。使用所提出的D锁存器设计了具有复位端以及具有置位和复位端的（单层和多层）电平敏感型并行输入并行输出（）移位寄存器、具有复位和置位/复位能力的（单层和多层）边沿敏感型移位寄存器以及并行输入串行输出（）移位寄存器。仿真表明，所提出的具有置位和复位端的电平敏感型移位寄存器有个单元，占用面积为13μm，延迟约为QCA时钟的个周期。此外，所提出的具有置位和复位引脚的边沿敏感型移位寄存器电路有个单元，占用面积为.17μm，延迟约为QCA时钟的个周期。所有设计和仿真结果均在QCADesigner软件中完成。
