An efficient new design of nano-scale comparator circuits using quantum-dot technology.

Traditional semiconductor-based technology has recently faced many issues, such as physical scalability constraints and short-channel properties. Much research on nano-scale designs has resulted in these flaws. Quantum-dot Cellular Automata () is a promising nanotechnology solution for solving -related issues. The squared cell is identified as the main feature of this technology. Also, a comparator is an essential electronic device that compares or currents. It is frequently employed to confirm whether an input has achieved a predefined value or not. So, the design of the QCA-based comparator is one of the interesting lines in recent studies. However, cell and area consumption limits the circuit design in the most relevant research. As a result, two efficient comparator circuits based on the inherent rules of quantum dots have been presented in this work. The proposed design employs quantum cells in a 04 μm compact layout space. Also, the proposed design uses  cells in a 19 μm2 compact layout area. These circuits, which are built across three layers of cells, remove the need for coplanar crossovers, ensuring accessible inputs and outputs. The presented comparator circuit uses majority gates with three inputs. The first output signal in comparator is generated after and in design after . evaluated the suggested circuits' practical accuracy, cost, and power. The results showed that the proposed designs are extremely efficient in cell and area consumption compared to the state-of-the-art designs.