Hsu Ting-Hao, Liu Hefei, Liao Han-Ting, Zhang Hongming, Zhao Jian, Hiramony Nishat Tasnim, Hossain Sushmit, Liu Zerui, Ye Jiacheng, Wang Han, Wu Wei
Ming Hsieh Department of Electrical and Computer Engineering, University of Southern California, Los Angeles, California 90089, United States.
John A. Paulson School of Engineering and Applied Sciences, Harvard University, Cambridge, Massachusetts 02138, United States.
ACS Nano. 2024 Dec 24;18(51):34986-34995. doi: 10.1021/acsnano.4c13295. Epub 2024 Dec 10.
The emergence of reconfigurable field effect transistors has introduced a more efficient method for realizing reconfigurable circuits, significantly lowering hardware overhead and enhancing versatility. However, these devices often suffer from asymmetric transfer curves, impacting logic gate performance and reliability. This work investigates the use of the van der Waals junction field effect transistor (JFET) for reconfigurable circuit applications. We present a reconfigurable JFET realized through WSe/MoS van der Waals integrated heterojunctions with an optimized polarity gate design that effectively addresses the issues of unmatched threshold voltages between n- and p- FETs while also anchoring threshold voltages and reducing subthreshold swing. A complementary reconfigurable JFET inverter with the proposed gate design was demonstrated, showcasing excellent switching characteristics, symmetric transfer characteristics, and reduced power consumption, achieving a noise margin of 96.3% and a high gain of 153.82. The study further demonstrates the construction of reconfigurable NOR/NAND and XOR/XNOR logic gates with symmetric profiles and sharp switching, underscoring the versatility and effectiveness of the proposed approach. These findings highlight the potential of WSe/MoS JFETs in advancing low-power, high-performance, reconfigurable electronic circuits within the CMOS framework.