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一种采用改进的栅极扩散注入（GDI）方法、基于32纳米技术的新型高能效4位吠陀乘法器。

A novel energy efficient 4-bit vedic multiplier using modified GDI approach at 32 nm technology.

作者信息

Nishanth Rao K, Sudha D, Ibrahim Khalaf Osamah, Abdulsaheb Ghaida Muttasher, Kumar Aruru Sai, Priyanka S Siva, Ouahada Khmaies, Hamam Habib

机构信息

Department of ECE, MLR Institute of Technology, Hyderabad, India.

Department of ECE, CMR College of Engineering and Technology, Telangana, India.

出版信息

Heliyon. 2024 May 20;10(10):e31120. doi: 10.1016/j.heliyon.2024.e31120. eCollection 2024 May 30.

DOI:10.1016/j.heliyon.2024.e31120
PMID:39670252
原文链接:https://pmc.ncbi.nlm.nih.gov/articles/PMC11637094/
Abstract

Multipliers are essential components within digital signal processing, arithmetic operations, and various computational tasks, making their design and optimization crucial for improving the efficiency and performance of integrated circuits. Among multiplier architectures, Vedic multipliers stand out due to their inherent efficiency and speed, derived from ancient Indian mathematical principles. This study presents a comprehensive analysis and comparison of 4-bit Vedic multiplier designs utilizing Gate Diffusion Input (GDI), Complementary Metal-Oxide-Semiconductor (CMOS), and Transmission Gate (TG) technologies, utilizing different adder architectures such as Ripple Carry Adder (RCA), and Carry Lookahead Adder (CLA), Carry Skip Adder (CSA). The objective is to explore the performance, area, and power consumption characteristics of these multipliers across different technologies and adder implementations. Each multiplier architecture is meticulously designed and optimized to leverage the unique features of the respective technology while adhering to the principles of Vedic mathematics. The designs are evaluated based on parameters such as transistor count, delay, power dissipation, and area. The results demonstrate the effectiveness of GDI technology in terms of in tems of delay, area, power and PDP when compared with other technologies. The 4-bit Vedic multiplier has been designed using 32 nm technology within Tanner EDA software tools.

摘要

乘法器是数字信号处理、算术运算及各种计算任务中的关键组件，因此其设计与优化对于提高集成电路的效率和性能至关重要。在乘法器架构中，吠陀乘法器因其源自古印度数学原理的固有高效性和速度而脱颖而出。本研究对采用栅极扩散输入（GDI）、互补金属氧化物半导体（CMOS）和传输门（TG）技术的4位吠陀乘法器设计进行了全面分析和比较，这些设计采用了不同的加法器架构，如行波进位加法器（RCA）、超前进位加法器（CLA）和进位跳跃加法器（CSA）。目的是探索这些乘法器在不同技术和加法器实现方式下的性能、面积和功耗特性。每种乘法器架构都经过精心设计和优化，以利用各自技术的独特特性，同时遵循吠陀数学原理。这些设计基于晶体管数量、延迟、功耗和面积等参数进行评估。结果表明，与其他技术相比，GDI技术在延迟、面积、功耗和功耗延迟积方面具有有效性。该4位吠陀乘法器是在Tanner EDA软件工具中使用32纳米技术设计的。

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