Experimental Investigation on the Electrical Properties of DPPT-TT Polymer Field-Effect Transistors Featuring Stair Gate Dielectric.

P-type polymer field-effect transistors (PFETs) achieve wide applications due to their environmental compatibility and inherent flexibility. However, the dielectric in PFETs presents a vulnerability that restricts the development of the advancement of p-type power devices and power integrated circuits with high voltage in power devices. In this work, we provide a novel method that employs p-type polymer DPPT-TT high-voltage PFETs with a stair gate dielectric structure (SGD) at both the source and drain sides. The breakdown voltage of this device is significantly increased, rising from 19 V to 80 V. This improvement is attributable to the SGD structure's ability to reduce the electric field between the source and drain. Although the step gate length () is 50 μm, the on-state resistance only increases by 20% in comparison to conventional devices. The step region contributes an additional resistance of 2.5 × 10 Ω/μm. The operational mechanism of the SGD PFET is demonstrated by TCAD simulations.