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用于基于氮化镓的绝缘栅器件的氧化铝栅极电介质技术现状

Status of Aluminum Oxide Gate Dielectric Technology for Insulated-Gate GaN-Based Devices.

作者信息

Calzolaro Anthony, Mikolajick Thomas, Wachowiak Andre

机构信息

Nanoelectronics, TU Dresden, D-01062 Dresden, Germany.

NaMLab gGmbH, Nöthnitzer Str. 64a, D-01187 Dresden, Germany.

出版信息

Materials (Basel). 2022 Jan 21;15(3):791. doi: 10.3390/ma15030791.

Abstract

Insulated-gate GaN-based transistors can fulfill the emerging demands for the future generation of highly efficient electronics for high-frequency, high-power and high-temperature applications. However, in contrast to Si-based devices, the introduction of an insulator on (Al)GaN is complicated by the absence of a high-quality native oxide for GaN. Trap states located at the insulator/(Al)GaN interface and within the dielectric can strongly affect the device performance. In particular, although AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) provide superior properties in terms of gate leakage currents compared to Schottky-gate HEMTs, the presence of an additional dielectric can induce threshold voltage instabilities. Similarly, the presence of trap states can be detrimental for the operational stability and reliability of other architectures of GaN devices employing a dielectric layer, such as hybrid MIS-FETs, trench MIS-FETs and vertical FinFETs. In this regard, the minimization of trap states is of critical importance to the advent of different insulated-gate GaN-based devices. Among the various dielectrics, aluminum oxide (AlO) is very attractive as a gate dielectric due to its large bandgap and band offsets to (Al)GaN, relatively high dielectric constant, high breakdown electric field as well as thermal and chemical stability against (Al)GaN. Additionally, although significant amounts of trap states are still present in the bulk AlO and at the AlO/(Al)GaN interface, the current technological progress in the atomic layer deposition (ALD) process has already enabled the deposition of promising high-quality, uniform and conformal AlO films to gate structures in GaN transistors. In this context, this paper first reviews the current status of gate dielectric technology using AlO for GaN-based devices, focusing on the recent progress in engineering high-quality ALD-AlO/(Al)GaN interfaces and on the performance of AlO-gated GaN-based MIS-HEMTs for power switching applications. Afterwards, novel emerging concepts using the AlO-based gate dielectric technology are introduced. Finally, the recent status of nitride-based materials emerging as other gate dielectrics is briefly reviewed.

摘要

基于绝缘栅的氮化镓晶体管能够满足未来对用于高频、高功率和高温应用的高效电子器件的新需求。然而,与基于硅的器件不同,在(铝)氮化镓上引入绝缘体因氮化镓缺乏高质量的原生氧化物而变得复杂。位于绝缘体/(铝)氮化镓界面以及电介质内部的陷阱态会强烈影响器件性能。特别是,尽管与肖特基栅高电子迁移率晶体管相比,铝镓氮/氮化镓金属 - 绝缘体 - 半导体高电子迁移率晶体管(MIS - HEMT)在栅极漏电流方面具有优越性能,但额外电介质的存在会引发阈值电压不稳定性。同样,陷阱态的存在对于采用介电层的其他氮化镓器件架构(如混合MIS - FET、沟槽MIS - FET和垂直鳍式场效应晶体管)的操作稳定性和可靠性可能是有害的。在这方面,将陷阱态最小化对于不同基于绝缘栅的氮化镓器件的出现至关重要。在各种电介质中,氧化铝(AlO)作为栅极电介质非常具有吸引力,因为它具有大的带隙和与(铝)氮化镓的带隙偏移、相对较高的介电常数、高击穿电场以及对(铝)氮化镓的热稳定性和化学稳定性。此外,尽管在块状氧化铝以及氧化铝/(铝)氮化镓界面中仍然存在大量陷阱态,但原子层沉积(ALD)工艺目前的技术进展已经能够在氮化镓晶体管的栅极结构上沉积出有前景的高质量、均匀且保形的氧化铝薄膜。在此背景下,本文首先回顾了使用氧化铝作为基于氮化镓器件的栅极电介质技术的现状,重点关注在工程高质量ALD - AlO/(铝)氮化镓界面方面的最新进展以及用于功率开关应用的氧化铝栅极氮化镓基MIS - HEMT的性能。之后,介绍了使用基于氧化铝的栅极电介质技术的新兴概念。最后,简要回顾了作为其他栅极电介质出现的氮化物基材料的最新状况。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/f74a/8837061/4968f24f1e53/materials-15-00791-g001.jpg

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