Onizawa Naoya, Hanyu Takahiro
Research Institute of Electrical Communication, Tohoku University, Sendai, 980-8577, Japan.
Sci Rep. 2025 Feb 19;15(1):6118. doi: 10.1038/s41598-025-90520-3.
Probabilistic computing using probabilistic bits (p-bits) presents an efficient alternative to traditional CMOS logic for complex problem-solving, including simulated annealing and machine learning. Realizing p-bits with emerging devices such as magnetic tunnel junctions introduces device variability, which was expected to negatively impact computational performance. However, this study reveals an unexpected finding: device variability can not only degrade but also enhance algorithm performance, particularly by leveraging timing variability. This paper introduces a GPU-accelerated, open-source simulated annealing framework based on p-bits that models key device variability factors-timing, intensity, and offset-to reflect real-world device behavior. Through CUDA-based simulations, our approach achieves a two-order magnitude speedup over CPU implementations on the MAX-CUT benchmark with problem sizes ranging from 800 to 20,000 nodes. By providing a scalable and accessible tool, this framework aims to advance research in probabilistic computing, enabling optimization applications in diverse fields.
使用概率比特（p比特）的概率计算为解决复杂问题（包括模拟退火和机器学习）提供了一种高效的替代传统CMOS逻辑的方法。利用诸如磁性隧道结等新兴器件实现p比特会引入器件变异性，这原本预计会对计算性能产生负面影响。然而，这项研究揭示了一个意想不到的发现：器件变异性不仅会降低算法性能，还可能增强算法性能，特别是通过利用时序变异性。本文介绍了一种基于p比特的GPU加速开源模拟退火框架，该框架对关键器件变异性因素——时序、强度和偏移进行建模，以反映实际器件行为。通过基于CUDA的模拟，我们的方法在MAX-CUT基准测试中，对于节点数从800到20000的问题规模，比CPU实现方式实现了两个数量级的加速。通过提供一个可扩展且易于使用的工具，该框架旨在推动概率计算研究，实现不同领域的优化应用。
