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通过原子层沉积(ALD)制备的中间层修饰4H-SiC MOS电容器以降低界面态密度

Reduction of Interface State Density in 4H-SiC MOS Capacitors Modified by ALD-Deposited Interlayers.

作者信息

Wang Zhenyu, Bai Zhaopeng, Guo Yunduo, Ding Chengxi, Huang Qimin, Gu Lin, Shen Yi, Zhang Qingchun, Ma Hongping

机构信息

Institute of Wide Bandgap Semiconductors and Future Lighting, Academy for Engineering & Technology, Fudan University, Shanghai 200433, China.

Shanghai Research Center for Silicon Carbide Power Devices Engineering & Technology, Fudan University, Shanghai 200433, China.

出版信息

Nanomaterials (Basel). 2025 Apr 5;15(7):555. doi: 10.3390/nano15070555.

DOI:10.3390/nano15070555
PMID:40214599
原文链接:https://pmc.ncbi.nlm.nih.gov/articles/PMC11990617/
Abstract

This study proposed an innovative method for growing gate oxide on silicon carbide (SiC), where silicon oxide (SiO) was fabricated on a deposited AlO layer, achieving high quality gate oxide. A thin AlO passivation layer was deposited via atomic layer deposition (ALD), followed by Si deposition and reoxidation to fabricate a MOS structure. The effects of different ALD growth cycles on the interface chemical composition, trap density, breakdown characteristics, and bias stress stability of the MOS capacitors were systematically investigated. X-ray photoelectron spectroscopy (XPS) analyses revealed that an ALD AlO passivation layer with 10 growth cycles effectively suppresses the formation of the proportion of Si-OC bonds. Additionally, the SiO/AlO/SiC gate stack with 10 ALD growth cycles exhibited optimal electrical properties, including a minimum interface state density () value of 3 × 10 cm eV and a breakdown field () of 10.9 MV/cm. We also systematically analyzed the bias stress stability of the capacitors at room temperature and elevated temperatures. Analysis of flat-band voltage (Δ) and midgap voltage (Δ) hysteresis after high-temperature positive and negative bias stress demonstrated that incorporating a thin AlO layer at the interface is the key factor in enhancing the stability of and midgap voltage .

摘要

本研究提出了一种在碳化硅(SiC)上生长栅氧化层的创新方法,即在沉积的AlO层上制备氧化硅(SiO),从而获得高质量的栅氧化层。通过原子层沉积(ALD)沉积一层薄的AlO钝化层,随后进行Si沉积和再氧化以制造MOS结构。系统地研究了不同ALD生长周期对MOS电容器的界面化学成分、陷阱密度、击穿特性和偏置应力稳定性的影响。X射线光电子能谱(XPS)分析表明,具有10个生长周期的ALD AlO钝化层有效地抑制了Si-OC键比例的形成。此外,具有10个ALD生长周期的SiO/AlO/SiC栅堆叠表现出最佳的电学性能,包括最小界面态密度()值为3×10 cm eV以及击穿场强()为10.9 MV/cm。我们还系统地分析了电容器在室温和高温下的偏置应力稳定性。对高温正负偏置应力后的平带电压(Δ)和带隙中点电压(Δ)滞后现象的分析表明,在界面处引入薄的AlO层是提高和带隙中点电压稳定性的关键因素。

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本文引用的文献

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2
Reliability and Stability Improvement of MOS Capacitors via Nitrogen-Hydrogen Mixed Plasma Pretreatment for SiC Surfaces.通过氮氢混合等离子体预处理改善碳化硅表面 MOS 电容器的可靠性和稳定性。
ACS Appl Mater Interfaces. 2023 Apr 12;15(14):18537-18549. doi: 10.1021/acsami.3c00995. Epub 2023 Mar 28.
3
Structural and Insulating Behaviour of High-Permittivity Binary Oxide Thin Films for Silicon Carbide and Gallium Nitride Electronic Devices.
用于碳化硅和氮化镓电子器件的高介电常数二元氧化物薄膜的结构与绝缘行为
Materials (Basel). 2022 Jan 22;15(3):830. doi: 10.3390/ma15030830.
4
Improved electrical performance of a sol-gel IGZO transistor with high-k AlO gate dielectric achieved by post annealing.通过后退火实现具有高k AlO栅极电介质的溶胶-凝胶IGZO晶体管的电学性能改善。
Nano Converg. 2019 Jul 22;6(1):24. doi: 10.1186/s40580-019-0194-1.