Reduction of Interface State Density in 4H-SiC MOS Capacitors Modified by ALD-Deposited Interlayers.

This study proposed an innovative method for growing gate oxide on silicon carbide (SiC), where silicon oxide (SiO) was fabricated on a deposited AlO layer, achieving high quality gate oxide. A thin AlO passivation layer was deposited via atomic layer deposition (ALD), followed by Si deposition and reoxidation to fabricate a MOS structure. The effects of different ALD growth cycles on the interface chemical composition, trap density, breakdown characteristics, and bias stress stability of the MOS capacitors were systematically investigated. X-ray photoelectron spectroscopy (XPS) analyses revealed that an ALD AlO passivation layer with 10 growth cycles effectively suppresses the formation of the proportion of Si-OC bonds. Additionally, the SiO/AlO/SiC gate stack with 10 ALD growth cycles exhibited optimal electrical properties, including a minimum interface state density () value of 3 × 10 cm eV and a breakdown field () of 10.9 MV/cm. We also systematically analyzed the bias stress stability of the capacitors at room temperature and elevated temperatures. Analysis of flat-band voltage (Δ) and midgap voltage (Δ) hysteresis after high-temperature positive and negative bias stress demonstrated that incorporating a thin AlO layer at the interface is the key factor in enhancing the stability of and midgap voltage .