Huang Qimin, Guo Yunduo, Wang Anfeng, Bai Zhaopeng, Gu Lin, Wang Zhenyu, Ding Chengxi, Shen Yi, Ma Hongping, Zhang Qingchun
Institute of Wide Bandgap Semiconductors and Future Lighting, Academy for Engineering & Technology, Fudan University, Shanghai 200433, China.
Shanghai Research Center for Silicon Carbide Power Devices Engineering & Technology, Fudan University, Shanghai 200433, China.
Materials (Basel). 2025 Apr 10;18(8):1741. doi: 10.3390/ma18081741.
The transition of SiC MOSFET structure from planar to trench-based architectures requires the optimization of gate dielectric layers to improve device performance. This study utilizes a range of characterization techniques to explore the interfacial properties of ZrO and SiO/ZrO gate dielectric films, grown via atomic layer deposition (ALD) in SiC epitaxial trench structures to assess their performance and suitability for device applications. Scanning electron microscopy (SEM) and atomic force microscopy (AFM) measurements showed the deposition of smooth film morphologies with roughness below 1 nm for both ZrO and SiO/ZrO gate dielectrics, while SE measurements revealed comparable physical thicknesses of 40.73 nm for ZrO and 41.55 nm for SiO/ZrO. X-ray photoelectron spectroscopy (XPS) shows that in SiO/ZrO thin films, the binding energies of Zr 3d and Zr 3d peaks shift upward compared to pure ZrO. Electrical characterization showed an enhancement of (3.76 to 5.78 MV·cm) and a decrease of (1.94 to 2.09 × 10 A·cm) for the SiO/ZrO stacks. Conduction mechanism analysis identified suppressed Schottky emission in the stacked film. This indicates that the incorporation of a thin SiO layer effectively mitigates the small bandgap offset, enhances the breakdown electric field, reduces leakage current, and improves device performance.
碳化硅金属氧化物半导体场效应晶体管（SiC MOSFET）结构从平面架构向基于沟槽的架构转变，需要优化栅极介电层以提高器件性能。本研究利用一系列表征技术，探索通过原子层沉积（ALD）在碳化硅外延沟槽结构中生长的氧化锆（ZrO）和二氧化硅/氧化锆（SiO/ZrO）栅极介电薄膜的界面特性，以评估它们的性能及对器件应用的适用性。扫描电子显微镜（SEM）和原子力显微镜（AFM）测量结果表明，ZrO和SiO/ZrO栅极电介质均沉积出表面光滑的薄膜形态，粗糙度低于1 nm，而扫描电子（SE）测量显示ZrO的物理厚度为40.73 nm，SiO/ZrO为41.55 nm，二者相当。X射线光电子能谱（XPS）表明，在SiO/ZrO薄膜中，Zr 3d和Zr 3d峰的结合能相对于纯ZrO向上移动。电学表征显示，SiO/ZrO堆叠结构的击穿电场增强（从3.76到5.78 MV·cm），漏电流密度降低（从1.94到2.09×10 A·cm）。传导机制分析确定堆叠薄膜中的肖特基发射受到抑制。这表明，掺入薄SiO层可有效减轻小的带隙偏移，增强击穿电场，降低漏电流，并改善器件性能。
