Interface Optimization and Performance Enhancement of ErO-Based MOS Devices by ALD-Derived AlO Passivation Layers and Annealing Treatment.

In this paper, the effect of atomic layer deposition (ALD)-derived AlO passivation layers and annealing temperatures on the interfacial chemistry and transport properties of sputtering-deposited ErO high-k gate dielectrics on Si substrate has been investigated. X-ray photoelectron spectroscopy (XPS) analyses have showed that the ALD-derived AlO passivation layer remarkably prevents the formation of the low-k hydroxides generated by moisture absorption of the gate oxide and greatly optimizes the gate dielectric properties. Electrical performance measurements of metal oxide semiconductor (MOS) capacitors with different gate stack order have revealed that the lowest leakage current density of 4.57 × 10 A/cm and the smallest interfacial density of states (Dit) of 2.38 × 10 cm eV have been achieved in the AlOErO/Si MOS capacitor, which can be attributed to the optimized interface chemistry. Further electrical measurements of annealed AlOErO/Si gate stacks at 450 °C have demonstrated superior dielectric properties with a leakage current density of 1.38 × 10 A/cm. At the same, the leakage current conduction mechanism of MOS devices under various stack structures is systematically investigated.