Wu Qiuju, Yu Qing, He Gang, Wang Wenhao, Lu Jinyu, Yao Bo, Liu Shiyan, Fang Zebo
Zhejiang Engineering Research Center of MEMS, Shaoxing University, Shaoxing 312000, China.
Semiconductor Manufacturing Electronics (Shaoxing) Corporation, Shaoxing 312000, China.
Nanomaterials (Basel). 2023 May 26;13(11):1740. doi: 10.3390/nano13111740.
In this paper, the effect of atomic layer deposition (ALD)-derived AlO passivation layers and annealing temperatures on the interfacial chemistry and transport properties of sputtering-deposited ErO high-k gate dielectrics on Si substrate has been investigated. X-ray photoelectron spectroscopy (XPS) analyses have showed that the ALD-derived AlO passivation layer remarkably prevents the formation of the low-k hydroxides generated by moisture absorption of the gate oxide and greatly optimizes the gate dielectric properties. Electrical performance measurements of metal oxide semiconductor (MOS) capacitors with different gate stack order have revealed that the lowest leakage current density of 4.57 × 10 A/cm and the smallest interfacial density of states (Dit) of 2.38 × 10 cm eV have been achieved in the AlOErO/Si MOS capacitor, which can be attributed to the optimized interface chemistry. Further electrical measurements of annealed AlOErO/Si gate stacks at 450 °C have demonstrated superior dielectric properties with a leakage current density of 1.38 × 10 A/cm. At the same, the leakage current conduction mechanism of MOS devices under various stack structures is systematically investigated.
本文研究了原子层沉积（ALD）法制备的AlO钝化层和退火温度对溅射沉积在Si衬底上的ErO高k栅介质的界面化学和输运性质的影响。X射线光电子能谱（XPS）分析表明，ALD法制备的AlO钝化层显著抑制了栅氧化物吸湿产生的低k氢氧化物的形成，并极大地优化了栅介质性能。对具有不同栅堆叠顺序的金属氧化物半导体（MOS）电容器的电学性能测量表明，AlO/ErO/Si MOS电容器实现了最低漏电流密度4.57×10⁻⁷ A/cm²和最小界面态密度（Dit）2.38×10¹¹ cm⁻² eV⁻¹，这可归因于优化的界面化学。对在450℃退火的AlO/ErO/Si栅堆叠进行的进一步电学测量表明，其具有优异的介电性能，漏电流密度为1.38×10⁻⁷ A/cm²。同时，系统研究了各种堆叠结构下MOS器件的漏电流传导机制。
