Eiroma Kim, Sneck Asko, Halonen Olli, Happonen Tuomas, Sandberg Henrik, Leppäniemi Jaakko
VTT Technical Research Centre of Finland, Ltd., Tietotie 3, FI-02150 Espoo, Finland.
VTT Technical Research Centre of Finland, Ltd., Kaitoväylä 1, FI-90590 Oulu, Finland.
ACS Appl Electron Mater. 2025 Apr 2;7(8):3511-3520. doi: 10.1021/acsaelm.5c00230. eCollection 2025 Apr 22.
High-resolution reverse-offset printing (ROP) is developed for miniaturization of printed electronics, resulting in a notable decrease in material usage compared to conventional printing processes. Two alternative ROP processes for patterning of metal conductors are available that are comparable in their cost per sample: direct nanoparticle (NP) printing (e.g., Ag and Cu) and patterning of vacuum-deposited metal (Ag, Al, Au, Cu, Ti, etc.) films using ROP printed polymer resist ink and the lift-off (LO) process. In this work, we focus on ROP of Cu NP ink followed by intense pulsed light (IPL) sintering and vacuum-deposited Cu patterned by ROP lift-off (LO). The good large-scale uniformity of the two processes is demonstrated by a grid of 300 individual thickness, sheet resistance, and resistivity measurement points with low variation over the 10 cm × 10 cm printed sample area. Sheet resistances of 0.56 ± 0.03 and 1.23 ± 0.05 Ω/□ are obtained at 113 and 40 nm thickness for Cu NP and Cu LO, respectively. Both processes show <5% thickness variation over a large area. A line-space (L/S) resolution of 2 μm is obtained for ROP patterned vacuum-deposited Cu having very low line edge roughness (LER) (∼60 nm), whereas for direct ROP printed Cu NP ink, the L/S resolution (2-4 μm) is limited by LER (∼900 nm) and influenced by the printed layer thickness. Based on the two fabrication routes, a flexible chip component assembly process is presented. Preliminary bending resistance results indicate that both ROP-based patterning processes yield a robust electrical interconnection between the ultrathin polyimide (PI) 5 mm × 5 mm chip and thermoplastic polyurethane (TPU). ROP shows promise as a scalable and sustainable patterning method for flexible ICs/chips that are assembled on flexible, stretchable, or biodegradable substrates and used, e.g., in wearable, large-scale sensing, and in environmental monitoring.
高分辨率反向胶版印刷（ROP）是为实现印刷电子产品的小型化而开发的，与传统印刷工艺相比，其材料用量显著减少。目前有两种用于金属导体图案化的ROP替代工艺，它们的每个样品成本相当：直接纳米颗粒（NP）印刷（如银和铜），以及使用ROP印刷的聚合物抗蚀剂油墨和剥离（LO）工艺对真空沉积的金属（银、铝、金、铜、钛等）薄膜进行图案化。在这项工作中，我们专注于铜NP油墨的ROP，随后进行强脉冲光（IPL）烧结，以及通过ROP剥离（LO）对真空沉积的铜进行图案化。在10 cm×10 cm的印刷样品区域内，通过300个单独的厚度、方块电阻和电阻率测量点组成的网格，证明了这两种工艺具有良好的大规模均匀性，变化很小。铜NP和铜LO在113和40 nm厚度下的方块电阻分别为0.56±0.03和1.23±0.05 Ω/□。两种工艺在大面积上的厚度变化均<5%。对于具有极低线条边缘粗糙度（LER）（约60 nm）的ROP图案化真空沉积铜，获得了2μm的线间距（L/S）分辨率，而对于直接ROP印刷的铜NP油墨，L/S分辨率（2 - 4μm）受LER（约900 nm）限制，并受印刷层厚度影响。基于这两种制造路线，提出了一种柔性芯片组件组装工艺。初步的抗弯曲结果表明，两种基于ROP的图案化工艺都能在超薄5 mm×5 mm聚酰亚胺（PI）芯片和热塑性聚氨酯（TPU）之间产生坚固的电气互连。ROP作为一种可扩展且可持续的图案化方法，有望用于在柔性、可拉伸或可生物降解基板上组装的柔性集成电路/芯片，例如用于可穿戴、大规模传感和环境监测等领域。
