Li Mengmeng, Niu Jiebin, Li Xufan, Tian Yue, Ding Chenming, Lu Congyan, Yang Zhenzhong, Huang Rong, Wang Lingfei, Yan He, Li Ling, Liu Ming
School of Integrated Circuits, University of Chinese Academy of Sciences, Beijing, 100049, P. R. China.
State Key Laboratory of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, 100029, P. R. China.
Adv Mater. 2025 Jul;37(28):e2420201. doi: 10.1002/adma.202420201. Epub 2025 May 6.
The scaling strategy is widely used to achieve much improved performance and reduced cost in a single chip with more devices for field-effect transistors (FETs) based on Si and state-of-the-art 2D materials. However, the downscaling of polymer FETs with high performance has not been achieved. Here both the body thickness scaling and channel length scaling strategies are employed, and demonstrate a 2.4-nm-thick polymer monolayer FET, where the shortest channel length (L) of 18 nm is achieved that is comparable to the smallest technology node (≈20 nm) for planar Si FETs. Such short-channel FETs, with good operational stability and reliability, exhibit only slightly lower field-effect mobility than the device with micrometer-long channel, but the on-state current density reaches 2.4 × 10 A µm. More importantly, a high intrinsic gate delay of 0.79 ps is achieved, while maintaining the on/off current ratio up to 10. Additionally, by increasing the thickness of gate dielectric a remarkable short channel effect is observed, which is in excellent agreement with natural scale length evaluated by the Scale Length Theory.